Convert CR In field to enum instead of single bit

diff --git a/src/soc/decoder/power_decoder.py b/src/soc/decoder/power_decoder.py
index 32cea4d12b9a9d3ee91c77633e5e3fcbe67c0919..ad405da6da39988fbaabfdd646f892e1cabacb9e 100644 (file)
--- a/src/soc/decoder/power_decoder.py
+++ b/src/soc/decoder/power_decoder.py
@@ -83,9 +83,11 @@ from collections import namedtuple
 from nmigen import Module, Elaboratable, Signal, Cat, Mux
 from nmigen.cli import rtlil
 from soc.decoder.power_enums import (Function, Form, InternalOp,
-                         In1Sel, In2Sel, In3Sel, OutSel, RC, LdstLen,
-                         CryIn, get_csv, single_bit_flags,
-                         get_signal_name, default_values)
+                                     In1Sel, In2Sel, In3Sel, OutSel,
+                                     RC, LdstLen, CryIn, get_csv,
+                                     single_bit_flags, CRInSel,
+                                     CROutSel, get_signal_name,
+                                     default_values)
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SigDecode, SignalBitRange
 
@@ -121,6 +123,7 @@ class PowerOp:
         self.in2_sel = Signal(In2Sel, reset_less=True)
         self.in3_sel = Signal(In3Sel, reset_less=True)
         self.out_sel = Signal(OutSel, reset_less=True)
+        self.cr_in = Signal(CRInSel, reset_less=True)
         self.ldst_len = Signal(LdstLen, reset_less=True)
         self.rc_sel = Signal(RC, reset_less=True)
         self.cry_in = Signal(CryIn, reset_less=True)
@@ -134,6 +137,9 @@ class PowerOp:
         # TODO: this conversion process from a dict to an object
         # should really be done using e.g. namedtuple and then
         # call eq not _eq
+        if row['CR in'] == '1':
+            import pdb; pdb.set_trace()
+            print(row)
         res = [self.function_unit.eq(Function[row['unit']]),
                self.form.eq(Form[row['form']]),
                self.internal_op.eq(InternalOp[row['internal op']]),
@@ -141,6 +147,7 @@ class PowerOp:
                self.in2_sel.eq(In2Sel[row['in2']]),
                self.in3_sel.eq(In3Sel[row['in3']]),
                self.out_sel.eq(OutSel[row['out']]),
+               self.cr_in.eq(CRInSel[row['CR in']]),
                self.ldst_len.eq(LdstLen[row['ldst len']]),
                self.rc_sel.eq(RC[row['rc']]),
                self.cry_in.eq(CryIn[row['cry in']]),
@@ -158,6 +165,7 @@ class PowerOp:
                self.in2_sel.eq(otherop.in2_sel),
                self.in3_sel.eq(otherop.in3_sel),
                self.out_sel.eq(otherop.out_sel),
+               self.cr_in.eq(otherop.cr_in),
                self.rc_sel.eq(otherop.rc_sel),
                self.ldst_len.eq(otherop.ldst_len),
                self.cry_in.eq(otherop.cry_in)]
@@ -172,6 +180,7 @@ class PowerOp:
                    self.in2_sel,
                    self.in3_sel,
                    self.out_sel,
+                   self.cr_in,
                    self.ldst_len,
                    self.rc_sel,
                    self.internal_op,

diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py
index 1b8395cc1a49f7937c814eeeae9c464ed1b3717a..bd9b6748822cf06d762e56bf7015f9a60ddd9b4a 100644 (file)
--- a/src/soc/decoder/power_enums.py
+++ b/src/soc/decoder/power_enums.py
@@ -23,13 +23,14 @@ def get_csv(name):
 
 
 # names of the fields in the tables that don't correspond to an enum
-single_bit_flags = ['CR in', 'CR out', 'inv A', 'inv out',
+single_bit_flags = ['CR out', 'inv A', 'inv out',
                     'cry out', 'BR', 'sgn ext', 'upd', 'rsrv', '32b',
                     'sgn', 'lk', 'sgl pipe']
 
 # default values for fields in the table
 default_values = {'unit': "NONE", 'internal op': "OP_ILLEGAL",
                   'in1': "RA", 'in2': 'NONE', 'in3': 'NONE', 'out': 'NONE',
+                  'CR in': 'NONE',
                   'ldst len': 'NONE',
                   'rc': 'NONE', 'cry in': 'ZERO', 'form': 'NONE'}
 
@@ -223,6 +224,24 @@ class CryIn(Enum):
     ONE = 1
     CA = 2
 
+@unique
+class CRInSel(Enum):
+    NONE = 0
+    CR0 = 1
+    BI = 2
+    BFA = 3
+    BA_BB = 4
+    BC = 5
+    WHOLE_REG = 6
+
+@unique
+class CROutSel(Enum):
+    NONE = 0
+    CR0 = 1
+    BF = 2
+    BT = 3
+    WHOLE_REG = 4
+
 
 # SPRs - Special-Purpose Registers.  See V3.0B Figure 18 p971 and
 # http://libre-riscv.org/openpower/isatables/sprs.csv

diff --git a/src/soc/decoder/test/test_power_decoder.py b/src/soc/decoder/test/test_power_decoder.py
index 6578fa1d2d82ee888f19f102b463b439f3d4fe65..c72ded066cdfc70f027bbe28821084484e8dfe76 100644 (file)
--- a/src/soc/decoder/test/test_power_decoder.py
+++ b/src/soc/decoder/test/test_power_decoder.py
@@ -6,9 +6,11 @@ import os
 import unittest
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_enums import (Function, InternalOp,
-                         In1Sel, In2Sel,In3Sel,
-                         OutSel, RC, LdstLen, CryIn, single_bit_flags,
-                         get_signal_name, get_csv)
+                                     In1Sel, In2Sel, In3Sel,
+                                     CRInSel, CROutSel,
+                                     OutSel, RC, LdstLen, CryIn,
+                                     single_bit_flags,
+                                     get_signal_name, get_csv)
 
 
 class DecoderTestCase(FHDLTestCase):
@@ -23,6 +25,7 @@ class DecoderTestCase(FHDLTestCase):
         in2_sel = Signal(In2Sel)
         in3_sel = Signal(In3Sel)
         out_sel = Signal(OutSel)
+        cr_in = Signal(CRInSel)
         rc_sel = Signal(RC)
         ldst_len = Signal(LdstLen)
         cry_in = Signal(CryIn)
@@ -38,6 +41,7 @@ class DecoderTestCase(FHDLTestCase):
                  in2_sel.eq(dut.op.in2_sel),
                  in3_sel.eq(dut.op.in3_sel),
                  out_sel.eq(dut.op.out_sel),
+                 cr_in.eq(dut.op.cr_in),
                  rc_sel.eq(dut.op.rc_sel),
                  ldst_len.eq(dut.op.ldst_len),
                  cry_in.eq(dut.op.cry_in),
@@ -75,6 +79,7 @@ class DecoderTestCase(FHDLTestCase):
                            (in2_sel, In2Sel, 'in2'),
                            (in3_sel, In3Sel, 'in3'),
                            (out_sel, OutSel, 'out'),
+                           (cr_in, CRInSel, 'CR in'),
                            (rc_sel, RC, 'rc'),
                            (cry_in, CryIn, 'cry in'),
                            (ldst_len, LdstLen, 'ldst len')]