no, do not assign clock to clock!

diff --git a/src/soc/litex/florent b/src/soc/litex/florent
index c709ad7d10143a32d9b36e4262f92da989035527..d7e76c5ba83b12e8466f16294ad052b62f679ce1 160000 (submodule)
--- a/src/soc/litex/florent
+++ b/src/soc/litex/florent
@@ -1 +1 @@
-Subproject commit c709ad7d10143a32d9b36e4262f92da989035527
+Subproject commit d7e76c5ba83b12e8466f16294ad052b62f679ce1

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 0cc7f428501afe4f9eff2b0e6bc8c851ae1194a5..4f559ce1ebc6316c613462c935c8826481e629e2 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -1299,10 +1299,8 @@ class TestIssuer(Elaboratable):
         # XXX BYPASS PLL XXX
         if False and self.pll_en:
             comb += intclk.eq(pllclk)
-            comb += dbgclk.eq(pllclk)
         else:
             comb += intclk.eq(ClockSignal())
-            comb += dbgclk.eq(ClockSignal())
         if self.ti.dbg_domain != 'sync':
             dbgclk = ClockSignal(self.ti.dbg_domain)
             comb += dbgclk.eq(intclk)