increase range of test values for extswsli

diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py
index f19ba4d3e618aace90f3ed62f299380a6c598644..ec35aaae02ad5cea03d46bd271f3edfa75e176f0 100644 (file)
--- a/src/soc/fu/shift_rot/test/test_pipe_caller.py
+++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py
@@ -153,7 +153,7 @@ class ShiftRotTestCase(FHDLTestCase):
             sh = random.randint(0, 63)
             lst = [f"extswsli 3, 1, {sh}"]
             initial_regs = [0] * 32
-            initial_regs[1] = random.randint(0, (1<<15)-1)
+            initial_regs[1] = random.randint(0, (1<<64)-1)
             self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_rlc(self):