TLB PLRUs are of TLB_WAY_BITS width

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 114aa0d2f70cb5ba9d979cfc2dd6f9c27c46f370..25325c5bb476a55df4baf38ee2db4f9864a829b4 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -654,7 +654,7 @@ class DCache(Elaboratable):
             return
         for i in range(TLB_SET_SIZE):
             # TLB PLRU interface
-            tlb_plru        = PLRU(WAY_BITS)
+            tlb_plru        = PLRU(TLB_WAY_BITS)
             setattr(m.submodules, "maybe_plru_%d" % i, tlb_plru)
             tlb_plru_acc_en = Signal()