clarify comment

diff --git a/src/experiment/compldst.py b/src/experiment/compldst.py
index e2fccf87e393e598ccd00a4bd14396b05b17a6ad..5754da5be82776c8753f273a1c0e8a2089f613c4 100644 (file)
--- a/src/experiment/compldst.py
+++ b/src/experiment/compldst.py
@@ -214,7 +214,7 @@ class LDSTCompUnit(Elaboratable):
             with m.If(~self.alu.p_ready_o):          # no ACK yet
                 m.d.comb += self.alu.p_valid_i.eq(1) # so indicate valid
 
-        # put the register directly onto the output
+        # put the register directly onto the output bus
         with m.If((self.go_wr_i & ~op_ldst) | (self.go_st_i & op_is_st)):
             comb += self.data_o.eq(data_r)