Fix test

diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py
index dcf5cad263a8978e4cc6d0a42fba4cec2d640cde..be41b5ccf1d73d7057834f7b09c6835320662161 100644 (file)
--- a/src/soc/decoder/power_enums.py
+++ b/src/soc/decoder/power_enums.py
@@ -4,7 +4,7 @@ import os
 import requests
 
 
-def get_csv(name):
+def download_wiki_file(name):
     file_dir = os.path.dirname(os.path.realpath(__file__))
     file_path = os.path.join(file_dir, name)
     if not os.path.isfile(file_path):
@@ -12,6 +12,11 @@ def get_csv(name):
         r = requests.get(url, allow_redirects=True)
         with open(file_path, 'w') as outfile:
             outfile.write(r.content.decode("utf-8"))
+    return file_path
+
+
+def get_csv(name):
+    file_path = download_wiki_file(name)
     with open(file_path, 'r') as csvfile:
         reader = csv.DictReader(csvfile)
         return list(reader)

diff --git a/src/soc/decoder/power_fields.py b/src/soc/decoder/power_fields.py
index 3457331ecee46632604bae7aec79917dc9291b91..a6352206056d14cbc4f018c32ae4ebb579345812 100644 (file)
--- a/src/soc/decoder/power_fields.py
+++ b/src/soc/decoder/power_fields.py
@@ -1,4 +1,5 @@
 from collections import OrderedDict, namedtuple
+from power_enums import download_wiki_file
 
 
 class BitRange(OrderedDict):
@@ -106,10 +107,10 @@ def decode_form(form):
 
 class DecodeFields:
 
-    def __init__(self, bitkls=BitRange, bitargs=(), fname="fields.txt"):
+    def __init__(self, bitkls=BitRange, bitargs=(), fname="fields.text"):
         self.bitkls = bitkls
         self.bitargs = bitargs
-        self.fname = fname
+        self.fname = download_wiki_file(fname)
 
     def create_specs(self):
         self.forms, self.instrs = self.decode_fields()

diff --git a/src/soc/decoder/test/test_power_decoder.py b/src/soc/decoder/test/test_power_decoder.py
index f64f4b962ee36c58e84369fccc8c6c17ca9c8be0..71b0fd91f8fa5baff953ecc2819cc43f3e0adccf 100644 (file)
--- a/src/soc/decoder/test/test_power_decoder.py
+++ b/src/soc/decoder/test/test_power_decoder.py
@@ -6,7 +6,7 @@ import sys
 import os
 import unittest
 sys.path.append("../")
-from power_decoder import (PowerDecoder, pdecode)
+from power_decoder import (create_pdecode)
 from power_enums import (Function, InternalOp, In1Sel, In2Sel, In3Sel,
                          OutSel, RC, LdstLen, CryIn, single_bit_flags,
                          get_signal_name, get_csv)
@@ -29,9 +29,7 @@ class DecoderTestCase(FHDLTestCase):
         cry_in = Signal(CryIn)
 
         # opcodes = get_csv(csvname)
-        # m.submodules.dut = dut = PowerDecoder(32, opcodes, bitsel=bitsel,
-        #                                       opint=opint, suffix=suffix)
-        m.submodules.dut = dut = pdecode
+        m.submodules.dut = dut = create_pdecode()
         comb += [dut.opcode_in.eq(opcode),
                  function_unit.eq(dut.op.function_unit),
                  in1_sel.eq(dut.op.in1_sel),
@@ -61,6 +59,13 @@ class DecoderTestCase(FHDLTestCase):
                     print(minor)
                     minorbits = minor[1]
                     yield opcode[minorbits[0]:minorbits[1]].eq(minor[0])
+                else:
+                    # OR 0, 0, 0  ; 0x60000000 is decoded as a NOP
+                    # If we're testing the OR instruction, make sure
+                    # that the instruction is not 0x60000000
+                    if int(op, 0) == 24:
+                        yield opcode[24:25].eq(0b11)
+
                 yield Delay(1e-6)
                 signals = [(function_unit, Function, 'unit'),
                            (internal_op, InternalOp, 'internal op'),
@@ -90,6 +95,7 @@ class DecoderTestCase(FHDLTestCase):
             sim.run()
 
     def generate_ilang(self):
+        pdecode = create_pdecode()
         vl = rtlil.convert(pdecode, ports=pdecode.ports())
         with open("decoder.il", "w") as f:
             f.write(vl)