LoadStore1 priv_mode was not being correctly picked up by the MMU

priv_mode needs to come from the original LD/ST request (or the
fetch), which was not happening

diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py
index 36836c674984cfc8c5ad870ed4a9eefcc9991d1b..081ff0194685169f14f5226a56a87f839a42bcd3 100644 (file)
--- a/src/soc/fu/ldst/loadstore.py
+++ b/src/soc/fu/ldst/loadstore.py
@@ -119,8 +119,6 @@ class LoadStore1(PortInterfaceBase):
         #self.atomic_last   = Signal()
         #self.rc            = Signal()
         self.nc            = Signal()              # non-cacheable access
-        self.virt_mode     = Signal()
-        self.priv_mode     = Signal()
         self.mode_32bit    = Signal() # XXX UNUSED AT PRESENT
         self.state         = Signal(State)
         self.instr_fault   = Signal()  # indicator to request i-cache MMU lookup
@@ -447,7 +445,7 @@ class LoadStore1(PortInterfaceBase):
         m.d.comb += m_out.valid.eq(mmureq)
         m.d.comb += m_out.iside.eq(self.instr_fault)
         m.d.comb += m_out.load.eq(ldst_r.load)
-        m.d.comb += m_out.priv.eq(self.priv_mode)
+        m.d.comb += m_out.priv.eq(ldst_r.priv_mode)
         # m_out.priv <= r.priv_mode; TODO
         m.d.comb += m_out.tlbie.eq(self.tlbie)
         # m_out.mtspr <= mmu_mtspr; # TODO

diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py
index 24be3f5402710bed1fb3a016e672ef12cc13671b..c1d4d74f9113f19b02ecf4d43395a9f738d36087 100644 (file)
--- a/src/soc/fu/mmu/fsm.py
+++ b/src/soc/fu/mmu/fsm.py
@@ -225,7 +225,6 @@ class FSMMMUStage(ControlBase):
                     # from accepting any other LD/ST requests.
                     comb += valid.eq(1)   # start "pulse"
                     comb += ldst.instr_fault.eq(blip)
-                    comb += ldst.priv_mode.eq(~msr_i[MSR.PR])
                     comb += ldst.maddr.eq(cia_i)
                     # XXX should not access this!
                     comb += done.eq(ldst.done)