Cleanup test_decoder_gas.py

diff --git a/src/soc/decoder/test/test_decoder_gas.py b/src/soc/decoder/test/test_decoder_gas.py
index 0f298a9e483675e3238cf090a5e8378725856376..8dd81ef29dbb6ab2ecec424754383e0593c9cba1 100644 (file)
--- a/src/soc/decoder/test/test_decoder_gas.py
+++ b/src/soc/decoder/test/test_decoder_gas.py
@@ -1,12 +1,10 @@
 from nmigen import Module, Signal
 from nmigen.back.pysim import Simulator, Delay
 from nmigen.test.utils import FHDLTestCase
-from nmigen.cli import rtlil
-import os
 import unittest
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_enums import (Function, InternalOp,
-                                     In1Sel, In2Sel,In3Sel,
+                                     In1Sel, In2Sel, In3Sel,
                                      OutSel, RC, LdstLen, CryIn,
                                      single_bit_flags, Form,
                                      get_signal_name, get_csv)
@@ -21,6 +19,7 @@ ops = {
     InternalOp.OP_AND: "and",
     InternalOp.OP_OR: "or"}
 
+
 class Register:
     def __init__(self, num):
         self.num = num
@@ -47,7 +46,7 @@ class DecoderTestCase(FHDLTestCase):
             args = ["powerpc64-linux-gnu-as",
                     "-o",
                     outfile.name]
-            p = subprocess.Popen(args, stdin = subprocess.PIPE)
+            p = subprocess.Popen(args, stdin=subprocess.PIPE)
             p.communicate(instruction.encode('utf-8'))
             assert(p.wait() == 0)
 
@@ -58,7 +57,7 @@ class DecoderTestCase(FHDLTestCase):
                         binfile.name]
                 subprocess.check_output(args)
                 binary = struct.unpack('>i', binfile.read(4))[0]
-                       return binary
+                return binary
 
     def test_decoder(self):
         m = Module()
@@ -68,7 +67,6 @@ class DecoderTestCase(FHDLTestCase):
         pdecode = create_pdecode()
 
         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
-        dec1 = pdecode2.dec
         comb += pdecode2.dec.opcode_in.eq(instruction)
 
         sim = Simulator(m)
@@ -80,9 +78,11 @@ class DecoderTestCase(FHDLTestCase):
                 r2 = Register(random.randrange(32))
                 r3 = Register(random.randrange(32))
 
-                instruction_str = self.generate_opcode_string(opcode, r1, r2, r3)
+                instruction_str = self.generate_opcode_string(
+                    opcode, r1, r2, r3)
                 print("instr", instruction_str.strip())
-                instruction_bin = self.get_assembled_instruction(instruction_str)
+                instruction_bin = self.get_assembled_instruction(
+                    instruction_str)
                 print("code", hex(instruction_bin), bin(instruction_bin))
 
                 yield instruction.eq(instruction_bin)
@@ -101,12 +101,11 @@ class DecoderTestCase(FHDLTestCase):
                 assert(r1sel == r1.num)
                 assert(r3sel == r3.num)
                 assert(r2sel == r2.num)
-                
+
         sim.add_process(process)
         with sim.write_vcd("gas.vcd", "gas.gtkw", traces=[pdecode2.ports()]):
             sim.run()
-            
-        
+
 
 if __name__ == "__main__":
     unittest.main()