set terminate if core terminate requested

rather than override what is in TestIssuerBase, which examines PC for
a DBG DMI Halt condition (stop_addr_o)

diff --git a/src/soc/simple/inorder.py b/src/soc/simple/inorder.py
index 510bd2dad70da2131f8a4456d3633d8d749a2a17..4edf92f120f2295e4a159939de1f0907913ce269 100644 (file)
--- a/src/soc/simple/inorder.py
+++ b/src/soc/simple/inorder.py
@@ -435,7 +435,8 @@ class TestIssuerInternalInOrder(TestIssuerBase):
         nia = Signal(64)
 
         # connect up debug signals
-        comb += dbg.terminate_i.eq(core.o.core_terminate_o)
+        with m.If(core.o.core_terminate_o):
+            comb += dbg.terminate_i.eq(1)
 
         # there are *THREE^WFOUR-if-SVP64-enabled* FSMs, fetch (32/64-bit)
         # issue, decode/execute, now joined by "Predicate fetch/calculate".

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 15391fe80c68fa3f8768c297761501c6adeea43a..156fce3cdf79ddc786804e6342a49533b12f3397 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -1415,7 +1415,8 @@ class TestIssuerInternal(TestIssuerBase):
         nia = Signal(64)
 
         # connect up debug signals
-        comb += dbg.terminate_i.eq(core.o.core_terminate_o)
+        with m.If(core.o.core_terminate_o):
+            comb += dbg.terminate_i.eq(1)
 
         # pass the prefix mode from Fetch to Issue, so the latter can loop
         # on VL==0