at the end of line (this requires dealing with requests coming in
while not idle...)
"""
- def __init__(self):
+ def __init__(self, pspec=None):
self.d_in = LoadStore1ToDCacheType("d_in")
self.d_out = DCacheToLoadStore1Type("d_out")
self.log_out = Signal(20)
+ # test if microwatt compatibility is to be enabled
+ self.microwatt_compat = (hasattr(pspec, "microwatt_compat") and
+ (pspec.microwatt_compat == True))
+
def stage_0(self, m, r0, r1, r0_full):
"""Latch the request in r0.req as long as we're not stalling
"""
# deal with litex not doing wishbone pipeline mode
# XXX in wrong way. FIFOs are needed in the SRAM test
# so that stb/ack match up. same thing done in icache.py
- comb += self.bus.stall.eq(self.bus.cyc & ~self.bus.ack)
+ if not self.microwatt_compat:
+ comb += self.bus.stall.eq(self.bus.cyc & ~self.bus.ack)
# Wire up wishbone request latch out of stage 1
comb += self.bus.we.eq(r1.wb.we)
def __init__(self, pspec):
+ # test if microwatt compatibility is to be enabled
+ self.microwatt_compat = (hasattr(pspec, "microwatt_compat") and
+ (pspec.microwatt_compat == True))
+ self.alt_reset = Signal(reset_less=True) # not connected yet (microwatt)
+
# test is SVP64 is to be enabled
self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
csd = DomainRenamer(self.core_domain)
dbd = DomainRenamer(self.dbg_domain)
- m.submodules.core = core = csd(self.core)
+ if self.microwatt_compat:
+ m.submodules.core = core = self.core
+ else:
+ m.submodules.core = core = csd(self.core)
# this _so_ needs sorting out. ICache is added down inside
# LoadStore1 and is already a submodule of LoadStore1
if not isinstance(self.imem, ICache):
m.submodules.imem = imem = csd(self.imem)
- m.submodules.dbg = dbg = dbd(self.dbg)
+ if self.microwatt_compat:
+ m.submodules.dbg = dbg = self.dbg
+ else:
+ m.submodules.dbg = dbg = dbd(self.dbg)
if self.jtag_en:
m.submodules.jtag = jtag = dbd(self.jtag)
# TODO: UART2GDB mux, here, from external pin
comb += self.state_w_sv.i_data.eq(self.new_svstate)
sync += self.sv_changed.eq(1)
+ # start renaming some of the ports to match microwatt
+ if self.microwatt_compat:
+ self.core.o.core_terminate_o.name = "terminated_out"
+ # names of DMI interface
+ self.dbg.dmi.addr_i.name = 'dmi_addr'
+ self.dbg.dmi.din.name = 'dmi_din'
+ self.dbg.dmi.dout.name = 'dmi_dout'
+ self.dbg.dmi.req_i.name = 'dmi_req'
+ self.dbg.dmi.we_i.name = 'dmi_wr'
+ self.dbg.dmi.ack_o.name = 'dmi_ack'
+ # wishbone instruction bus
+ ibus = self.imem.ibus
+ ibus.adr.name = 'wishbone_insn_out.adr'
+ ibus.dat_w.name = 'wishbone_insn_out.dat'
+ ibus.sel.name = 'wishbone_insn_out.sel'
+ ibus.cyc.name = 'wishbone_insn_out.cyc'
+ ibus.stb.name = 'wishbone_insn_out.stb'
+ ibus.we.name = 'wishbone_insn_out.we'
+ ibus.dat_r.name = 'wishbone_insn_in.dat'
+ ibus.ack.name = 'wishbone_insn_in.ack'
+ ibus.stall.name = 'wishbone_insn_in.stall'
+ # wishbone data bus
+ dbus = self.core.l0.cmpi.wb_bus()
+ dbus.adr.name = 'wishbone_data_out.adr'
+ dbus.dat_w.name = 'wishbone_data_out.dat'
+ dbus.sel.name = 'wishbone_data_out.sel'
+ dbus.cyc.name = 'wishbone_data_out.cyc'
+ dbus.stb.name = 'wishbone_data_out.stb'
+ dbus.we.name = 'wishbone_data_out.we'
+ dbus.dat_r.name = 'wishbone_data_in.dat'
+ dbus.ack.name = 'wishbone_data_in.ack'
+ dbus.stall.name = 'wishbone_data_in.stall'
+
return m
def __iter__(self):
return list(self)
def external_ports(self):
+ if self.microwatt_compat:
+ ports = [self.core.o.core_terminate_o,
+ self.alt_reset, # not connected yet
+ ClockSignal(),
+ ResetSignal(),
+ ]
+ ports += list(self.dbg.dmi.ports())
+ # for dbus/ibus microwatt, exclude err btw and cti
+ for name, sig in self.imem.ibus.fields.items():
+ if name not in ['err', 'bte', 'cti']:
+ ports.append(sig)
+ for name, sig in self.core.l0.cmpi.wb_bus().fields.items():
+ if name not in ['err', 'bte', 'cti']:
+ ports.append(sig)
+ return ports
+
ports = self.pc_i.ports()
ports = self.msr_i.ports()
ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
from openpower.consts import MSR
from soc.config.test.test_loadstore import TestMemPspec
-from soc.simple.issuer import TestIssuer
+from soc.simple.issuer import TestIssuer, TestIssuerInternal
if __name__ == '__main__':
parser.add_argument("--disable-svp64", dest='svp64', action="store_false",
help="disable SVP64",
default=False)
+ # create a module that's directly compatible as a drop-in replacement
+ # in microwatt.v
+ parser.add_argument("--microwatt-compat", dest='mwcompat',
+ action="store_true",
+ help="generate microwatt-compatible interface",
+ default=False)
args = parser.parse_args()
+ # convenience: set some defaults
+ if args.mwcompat:
+ args.pll = False
+ args.debug = 'dmi'
+ args.core = True
+ args.xics = False
+ args.gpio = False
+ args.sram4x4kblock = False
+ args.svp64 = False
+
print(args)
units = {'alu': 1,
sram4x4kblock=args.enable_sram4x4kblock, # add SRAMs
debug=args.debug, # set to jtag or dmi
svp64=args.svp64, # enable SVP64
- microwatt_mmu=args.mmu, # enable MMU
+ microwatt_mmu=args.mmu, # enable MMU
+ microwatt_compat=args.mwcompat, # microwatt compatible
units=units,
msr_reset=msr_reset)
+ if args.mwcompat:
+ pspec.core_domain = 'sync'
print("mmu", pspec.__dict__["microwatt_mmu"])
print("nocore", pspec.__dict__["nocore"])
print("use_pll", pspec.__dict__["use_pll"])
print("debug", pspec.__dict__["debug"])
print("SVP64", pspec.__dict__["svp64"])
+ print("Microwatt compatibility", pspec.__dict__["microwatt_compat"])
- dut = TestIssuer(pspec)
+ if args.mwcompat:
+ dut = TestIssuerInternal(pspec)
+ else:
+ dut = TestIssuer(pspec)
vl = verilog.convert(dut, ports=dut.external_ports(), name="test_issuer")
with open(args.output_filename, "w") as f:
projects / soc.git / commitdiff