raise interrupt on misaligned atomic LDST

diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py
index d13e525e6f5b7d9c3a179932da5f7920cabc2934..d0beddedbf6d4571d24dfdff0045a9deb59ef077 100644 (file)
--- a/src/soc/fu/ldst/loadstore.py
+++ b/src/soc/fu/ldst/loadstore.py
@@ -245,6 +245,8 @@ class LoadStore1(PortInterfaceBase):
         # check for LR/SC misalignment, used in set_rd/wr_addr above
         comb += self.lrsc_misalign.eq(((self.pi.data_len[0:3]-1) &
                                         self.req.raddr[0:3]).bool())
+        with m.If(self.lrsc_misalign & self.req.reserve):
+            m.d.comb += self.req.align_intr.eq(1)
 
         # create a blip (single pulse) on valid read/write request
         # this can be over-ridden in the FSM to get dcache to re-run