replace go_read/go_write with go_rd/go_wr

diff --git a/src/scoreboard/dependence_cell.py b/src/scoreboard/dependence_cell.py
index 18e8d75556ab0338e3021c81c52d587d01787063..5b7baea8c66f94af39b2c868c1daa5e3d1a6a05f 100644 (file)
--- a/src/scoreboard/dependence_cell.py
+++ b/src/scoreboard/dependence_cell.py
@@ -14,8 +14,8 @@ class DependenceCell(Elaboratable):
         self.src2_i = Signal(reset_less=True)     # oper2 in (top)
         self.issue_i = Signal(reset_less=True)    # Issue in (top)
 
-        self.go_write_i = Signal(reset_less=True) # Go Write in (left)
-        self.go_read_i = Signal(reset_less=True)  # Go Read in (left)
+        self.go_wr_i = Signal(reset_less=True) # Go Write in (left)
+        self.go_rd_i = Signal(reset_less=True)  # Go Read in (left)
 
         # for Register File Select Lines (vertical)
         self.dest_rsel_o = Signal(reset_less=True)  # dest reg sel (bottom)
@@ -33,17 +33,17 @@ class DependenceCell(Elaboratable):
         m.submodules.src1_l = src1_l = SRLatch()
         m.submodules.src2_l = src2_l = SRLatch()
 
-        # destination latch: reset on go_write HI, set on dest and issue
+        # destination latch: reset on go_wr HI, set on dest and issue
         m.d.comb += dest_l.s.eq(self.issue_i & self.dest_i)
-        m.d.comb += dest_l.r.eq(self.go_write_i)
+        m.d.comb += dest_l.r.eq(self.go_wr_i)
 
-        # src1 latch: reset on go_read HI, set on src1_i and issue
+        # src1 latch: reset on go_rd HI, set on src1_i and issue
         m.d.comb += src1_l.s.eq(self.issue_i & self.src1_i)
-        m.d.comb += src1_l.r.eq(self.go_read_i)
+        m.d.comb += src1_l.r.eq(self.go_rd_i)
 
-        # src2 latch: reset on go_read HI, set on op2_i and issue
+        # src2 latch: reset on go_rd HI, set on op2_i and issue
         m.d.comb += src2_l.s.eq(self.issue_i & self.src2_i)
-        m.d.comb += src2_l.r.eq(self.go_read_i)
+        m.d.comb += src2_l.r.eq(self.go_rd_i)
 
         # FU "Forward Progress" (read out horizontally)
         m.d.comb += self.dest_fwd_o.eq(dest_l.qn & self.dest_i)
@@ -51,9 +51,9 @@ class DependenceCell(Elaboratable):
         m.d.comb += self.src2_fwd_o.eq(src2_l.qn & self.src2_i)
 
         # Register File Select (read out vertically)
-        m.d.comb += self.dest_rsel_o.eq(dest_l.qn & self.go_write_i)
-        m.d.comb += self.src1_rsel_o.eq(src1_l.qn & self.go_read_i)
-        m.d.comb += self.src2_rsel_o.eq(src2_l.qn & self.go_read_i)
+        m.d.comb += self.dest_rsel_o.eq(dest_l.qn & self.go_wr_i)
+        m.d.comb += self.src1_rsel_o.eq(src1_l.qn & self.go_rd_i)
+        m.d.comb += self.src2_rsel_o.eq(src2_l.qn & self.go_rd_i)
 
         return m
 
@@ -62,8 +62,8 @@ class DependenceCell(Elaboratable):
         yield self.src1_i
         yield self.src2_i
         yield self.issue_i
-        yield self.go_write_i
-        yield self.go_read_i
+        yield self.go_wr_i
+        yield self.go_rd_i
         yield self.dest_rsel_o
         yield self.src1_rsel_o
         yield self.src2_rsel_o
@@ -88,13 +88,13 @@ def dcell_sim(dut):
     yield
     yield dut.issue_i.eq(0)
     yield
-    yield dut.go_read_i.eq(1)
+    yield dut.go_rd_i.eq(1)
     yield
-    yield dut.go_read_i.eq(0)
+    yield dut.go_rd_i.eq(0)
     yield
-    yield dut.go_write_i.eq(1)
+    yield dut.go_wr_i.eq(1)
     yield
-    yield dut.go_write_i.eq(0)
+    yield dut.go_wr_i.eq(0)
     yield
 
 def test_dcell():

diff --git a/src/scoreboard/fn_unit.py b/src/scoreboard/fn_unit.py
index 8474e2dc0696405cdf89a80d1b6485817e5ea9ff..bbb60ac588225306d3558d7609e863e7f7d4b6d0 100644 (file)
--- a/src/scoreboard/fn_unit.py
+++ b/src/scoreboard/fn_unit.py
@@ -50,8 +50,8 @@ class FnUnit(Elaboratable):
         self.src2_i = Signal(max=wid, reset_less=True) # oper2 R# in (top)
         self.issue_i = Signal(reset_less=True)    # Issue in (top)
 
-        self.go_write_i = Signal(reset_less=True) # Go Write in (left)
-        self.go_read_i = Signal(reset_less=True)  # Go Read in (left)
+        self.go_wr_i = Signal(reset_less=True) # Go Write in (left)
+        self.go_rd_i = Signal(reset_less=True)  # Go Read in (left)
         self.req_rel_i = Signal(reset_less=True)  # request release (left)
 
         self.g_xx_pend_i = Array(Signal(wid, reset_less=True, name="g_pend_i") \
@@ -124,13 +124,13 @@ class FnUnit(Elaboratable):
             m.d.comb += self.xx_pend_o[i].eq(0)  # initialise all array
             m.d.comb += self.writable_o[i].eq(0) # to zero
 
-        # go_write latch: reset on go_write HI, set on issue
+        # go_wr latch: reset on go_wr HI, set on issue
         m.d.comb += wr_l.s.eq(self.issue_i)
-        m.d.comb += wr_l.r.eq(self.go_write_i | recover)
+        m.d.comb += wr_l.r.eq(self.go_wr_i | recover)
 
-        # src1 latch: reset on go_read HI, set on issue
+        # src1 latch: reset on go_rd HI, set on issue
         m.d.comb += rd_l.s.eq(self.issue_i)
-        m.d.comb += rd_l.r.eq(self.go_read_i | recover)
+        m.d.comb += rd_l.r.eq(self.go_rd_i | recover)
 
         # dest decoder: write-pending out
         m.d.comb += dest_d.i.eq(self.dest_i)
@@ -166,8 +166,8 @@ class FnUnit(Elaboratable):
         yield self.src1_i
         yield self.src2_i
         yield self.issue_i
-        yield self.go_write_i
-        yield self.go_read_i
+        yield self.go_wr_i
+        yield self.go_rd_i
         yield self.req_rel_i
         yield from self.g_xx_pend_i
         yield self.g_wr_pend_i
@@ -296,13 +296,13 @@ def int_fn_unit_sim(dut):
     yield
     yield dut.issue_i.eq(0)
     yield
-    yield dut.go_read_i.eq(1)
+    yield dut.go_rd_i.eq(1)
     yield
-    yield dut.go_read_i.eq(0)
+    yield dut.go_rd_i.eq(0)
     yield
-    yield dut.go_write_i.eq(1)
+    yield dut.go_wr_i.eq(1)
     yield
-    yield dut.go_write_i.eq(0)
+    yield dut.go_wr_i.eq(0)
     yield
 
 def test_int_fn_unit():

diff --git a/src/scoreboard/fu_dep_cell.py b/src/scoreboard/fu_dep_cell.py
index 93ef28d3cbd82f609f585225960ce2ed06702169..250ba85b91cc74f598328f7b56e324aabc5cd1e1 100644 (file)
--- a/src/scoreboard/fu_dep_cell.py
+++ b/src/scoreboard/fu_dep_cell.py
@@ -13,8 +13,8 @@ class FUDependenceCell(Elaboratable):
         self.wr_pend_i = Signal(reset_less=True)     # write pending in (left)
         self.issue_i = Signal(reset_less=True)    # Issue in (top)
 
-        self.go_write_i = Signal(reset_less=True) # Go Write in (left)
-        self.go_read_i = Signal(reset_less=True)  # Go Read in (left)
+        self.go_wr_i = Signal(reset_less=True) # Go Write in (left)
+        self.go_rd_i = Signal(reset_less=True)  # Go Read in (left)
 
         # outputs (latched rd/wr pend)
         self.rd_pend_o = Signal(reset_less=True)   # read pending out (right)
@@ -25,13 +25,13 @@ class FUDependenceCell(Elaboratable):
         m.submodules.rd_l = rd_l = SRLatch()
         m.submodules.wr_l = wr_l = SRLatch()
 
-        # write latch: reset on go_write HI, set on write pending and issue
+        # write latch: reset on go_wr HI, set on write pending and issue
         m.d.comb += wr_l.s.eq(self.issue_i & self.wr_pend_i)
-        m.d.comb += wr_l.r.eq(self.go_write_i)
+        m.d.comb += wr_l.r.eq(self.go_wr_i)
 
-        # read latch: reset on go_read HI, set on read pending and issue
+        # read latch: reset on go_rd HI, set on read pending and issue
         m.d.comb += rd_l.s.eq(self.issue_i & self.rd_pend_i)
-        m.d.comb += rd_l.r.eq(self.go_read_i)
+        m.d.comb += rd_l.r.eq(self.go_rd_i)
 
         # Read/Write Pending Latches (read out horizontally)
         m.d.comb += self.wr_pend_o.eq(wr_l.qn)
@@ -43,8 +43,8 @@ class FUDependenceCell(Elaboratable):
         yield self.rd_pend_i
         yield self.wr_pend_i
         yield self.issue_i
-        yield self.go_write_i
-        yield self.go_read_i
+        yield self.go_wr_i
+        yield self.go_rd_i
         yield self.rd_pend_o
         yield self.wr_pend_o
                 
@@ -63,13 +63,13 @@ def dcell_sim(dut):
     yield
     yield dut.issue_i.eq(0)
     yield
-    yield dut.go_read_i.eq(1)
+    yield dut.go_rd_i.eq(1)
     yield
-    yield dut.go_read_i.eq(0)
+    yield dut.go_rd_i.eq(0)
     yield
-    yield dut.go_write_i.eq(1)
+    yield dut.go_wr_i.eq(1)
     yield
-    yield dut.go_write_i.eq(0)
+    yield dut.go_wr_i.eq(0)
     yield
 
 def test_dcell():

diff --git a/src/scoreboard/fu_fu_matrix.py b/src/scoreboard/fu_fu_matrix.py
index b558927c8b13581a0e2221075413117047db26c0..a73cde9c2671d83d8915dd4d344b865bcb1c9138 100644 (file)
--- a/src/scoreboard/fu_fu_matrix.py
+++ b/src/scoreboard/fu_fu_matrix.py
@@ -23,8 +23,8 @@ class FUFUDepMatrix(Elaboratable):
         self.wr_pend_i = Signal(n_fu_row, reset_less=True) # Wr pending (left)
         self.issue_i = Signal(n_fu_col, reset_less=True)    # Issue in (top)
 
-        self.go_write_i = Signal(n_fu_row, reset_less=True) # Go Write in (left)
-        self.go_read_i = Signal(n_fu_row, reset_less=True)  # Go Read in (left)
+        self.go_wr_i = Signal(n_fu_row, reset_less=True) # Go Write in (left)
+        self.go_rd_i = Signal(n_fu_row, reset_less=True)  # Go Read in (left)
 
         # for Function Unit Readable/Writable (horizontal)
         self.readable_o = Signal(n_fu_col, reset_less=True) # readable (bot)
@@ -88,23 +88,23 @@ class FUFUDepMatrix(Elaboratable):
             m.d.comb += Cat(*issue_i).eq(self.issue_i)
 
         # ---
-        # connect Matrix go_read_i/go_write_i to module readable/writable
+        # connect Matrix go_rd_i/go_wr_i to module readable/writable
         # ---
         for x in range(self.n_fu_col):
-            go_read_i = []
-            go_write_i = []
+            go_rd_i = []
+            go_wr_i = []
             rd_pend_i = []
             wr_pend_i = []
             for y in range(self.n_fu_row):
                 dc = dm[x][y]
-                # accumulate cell rd_pend/wr_pend/go_read/go_write
+                # accumulate cell rd_pend/wr_pend/go_rd/go_wr
                 rd_pend_i.append(dc.rd_pend_i)
                 wr_pend_i.append(dc.wr_pend_i)
-                go_read_i.append(dc.go_read_i)
-                go_write_i.append(dc.go_write_i)
+                go_rd_i.append(dc.go_rd_i)
+                go_wr_i.append(dc.go_wr_i)
             # wire up inputs from module to row cell inputs (Cat is gooood)
-            m.d.comb += [Cat(*go_read_i).eq(self.go_read_i),
-                         Cat(*go_write_i).eq(self.go_write_i),
+            m.d.comb += [Cat(*go_rd_i).eq(self.go_rd_i),
+                         Cat(*go_wr_i).eq(self.go_wr_i),
                          Cat(*rd_pend_i).eq(self.rd_pend_i),
                          Cat(*wr_pend_i).eq(self.wr_pend_i),
                         ]
@@ -115,8 +115,8 @@ class FUFUDepMatrix(Elaboratable):
         yield self.rd_pend_i
         yield self.wr_pend_i
         yield self.issue_i
-        yield self.go_write_i
-        yield self.go_read_i
+        yield self.go_wr_i
+        yield self.go_rd_i
         yield self.readable_o
         yield self.writable_o
                 
@@ -136,13 +136,13 @@ def d_matrix_sim(dut):
     yield
     yield dut.issue_i.eq(0)
     yield
-    yield dut.go_read_i.eq(1)
+    yield dut.go_rd_i.eq(1)
     yield
-    yield dut.go_read_i.eq(0)
+    yield dut.go_rd_i.eq(0)
     yield
-    yield dut.go_write_i.eq(1)
+    yield dut.go_wr_i.eq(1)
     yield
-    yield dut.go_write_i.eq(0)
+    yield dut.go_wr_i.eq(0)
     yield
 
 def test_fu_fu_matrix():

diff --git a/src/scoreboard/fu_reg_matrix.py b/src/scoreboard/fu_reg_matrix.py
index 9997d6e2f846206873f05536b4dc0963e6e0c8c1..f28e366f932373a8e92a3f3b74ef8629e7b3ddfd 100644 (file)
--- a/src/scoreboard/fu_reg_matrix.py
+++ b/src/scoreboard/fu_reg_matrix.py
@@ -36,8 +36,8 @@ class FURegDepMatrix(Elaboratable):
         self.src2_i = Signal(n_reg_col, reset_less=True)     # oper2 in (top)
         self.issue_i = Signal(n_reg_col, reset_less=True)    # Issue in (top)
 
-        self.go_write_i = Signal(n_fu_row, reset_less=True) # Go Write in (left)
-        self.go_read_i = Signal(n_fu_row, reset_less=True)  # Go Read in (left)
+        self.go_wr_i = Signal(n_fu_row, reset_less=True) # Go Write in (left)
+        self.go_rd_i = Signal(n_fu_row, reset_less=True)  # Go Read in (left)
 
         # for Register File Select Lines (horizontal), per-reg
         self.dest_rsel_o = Signal(n_reg_col, reset_less=True) # dest reg (bot)
@@ -158,19 +158,19 @@ class FURegDepMatrix(Elaboratable):
                         ]
 
         # ---
-        # connect Dependency Matrix go_read_i/go_write_i to module go_rd/go_wr
+        # connect Dependency Matrix go_rd_i/go_wr_i to module go_rd/go_wr
         # ---
         for fu in range(self.n_fu_row):
-            go_read_i = []
-            go_write_i = []
+            go_rd_i = []
+            go_wr_i = []
             for rn in range(self.n_reg_col):
                 dc = dm[rn][fu]
                 # accumulate cell fwd outputs for dest/src1/src2 
-                go_read_i.append(dc.go_read_i)
-                go_write_i.append(dc.go_write_i)
+                go_rd_i.append(dc.go_rd_i)
+                go_wr_i.append(dc.go_wr_i)
             # wire up inputs from module to row cell inputs (Cat is gooood)
-            m.d.comb += [Cat(*go_read_i).eq(self.go_read_i),
-                         Cat(*go_write_i).eq(self.go_write_i),
+            m.d.comb += [Cat(*go_rd_i).eq(self.go_rd_i),
+                         Cat(*go_wr_i).eq(self.go_wr_i),
                         ]
 
         return m
@@ -180,8 +180,8 @@ class FURegDepMatrix(Elaboratable):
         yield self.src1_i
         yield self.src2_i
         yield self.issue_i
-        yield self.go_write_i
-        yield self.go_read_i
+        yield self.go_wr_i
+        yield self.go_rd_i
         yield self.dest_rsel_o
         yield self.src1_rsel_o
         yield self.src2_rsel_o
@@ -204,13 +204,13 @@ def d_matrix_sim(dut):
     yield
     yield dut.issue_i.eq(0)
     yield
-    yield dut.go_read_i.eq(1)
+    yield dut.go_rd_i.eq(1)
     yield
-    yield dut.go_read_i.eq(0)
+    yield dut.go_rd_i.eq(0)
     yield
-    yield dut.go_write_i.eq(1)
+    yield dut.go_wr_i.eq(1)
     yield
-    yield dut.go_write_i.eq(0)
+    yield dut.go_wr_i.eq(0)
     yield
 
 def test_d_matrix():

diff --git a/src/scoreboard/global_pending.py b/src/scoreboard/global_pending.py
index 50e43378e76e112f22d548878b21ed218215615c..a5d4db1bd5dab8c5ca5d5f7a66847b7b20997588 100644 (file)
--- a/src/scoreboard/global_pending.py
+++ b/src/scoreboard/global_pending.py
@@ -69,13 +69,13 @@ def g_vec_sim(dut):
     yield
     yield dut.issue_i.eq(0)
     yield
-    yield dut.go_read_i.eq(1)
+    yield dut.go_rd_i.eq(1)
     yield
-    yield dut.go_read_i.eq(0)
+    yield dut.go_rd_i.eq(0)
     yield
-    yield dut.go_write_i.eq(1)
+    yield dut.go_wr_i.eq(1)
     yield
-    yield dut.go_write_i.eq(0)
+    yield dut.go_wr_i.eq(0)
     yield
 
 def test_g_vec():

diff --git a/src/scoreboard/group_picker.py b/src/scoreboard/group_picker.py
index 8f959a188ccb72c4799946826e7d732e9a4f2a57..78f834145b56343033e2abdeac29ff2769fc1584 100644 (file)
--- a/src/scoreboard/group_picker.py
+++ b/src/scoreboard/group_picker.py
@@ -90,13 +90,13 @@ def grp_pick_sim(dut):
     yield
     yield dut.issue_i.eq(0)
     yield
-    yield dut.go_read_i.eq(1)
+    yield dut.go_rd_i.eq(1)
     yield
-    yield dut.go_read_i.eq(0)
+    yield dut.go_rd_i.eq(0)
     yield
-    yield dut.go_write_i.eq(1)
+    yield dut.go_wr_i.eq(1)
     yield
-    yield dut.go_write_i.eq(0)
+    yield dut.go_wr_i.eq(0)
     yield
 
 def test_grp_pick():

diff --git a/src/scoreboard/issue_unit.py b/src/scoreboard/issue_unit.py
index 7b01e8f48fcd7d25769e9c7aef3c01b622e7a277..a677bd6eb63be5d1abd7d61b7e35019333a8de96 100644 (file)
--- a/src/scoreboard/issue_unit.py
+++ b/src/scoreboard/issue_unit.py
@@ -117,13 +117,13 @@ def issue_unit_sim(dut):
     yield
     yield dut.issue_i.eq(0)
     yield
-    yield dut.go_read_i.eq(1)
+    yield dut.go_rd_i.eq(1)
     yield
-    yield dut.go_read_i.eq(0)
+    yield dut.go_rd_i.eq(0)
     yield
-    yield dut.go_write_i.eq(1)
+    yield dut.go_wr_i.eq(1)
     yield
-    yield dut.go_write_i.eq(0)
+    yield dut.go_wr_i.eq(0)
     yield
 
 def test_issue_unit():

diff --git a/src/scoreboard/ldst_dep_cell.py b/src/scoreboard/ldst_dep_cell.py
index 40e1ffbc4d8d724961ec46da29569e12ae64ce85..c865bdd8ce0a9b9ee42aca09c35395acee69631c 100644 (file)
--- a/src/scoreboard/ldst_dep_cell.py
+++ b/src/scoreboard/ldst_dep_cell.py
@@ -74,13 +74,13 @@ def dcell_sim(dut):
     yield
     yield dut.issue_i.eq(0)
     yield
-    yield dut.go_read_i.eq(1)
+    yield dut.go_rd_i.eq(1)
     yield
-    yield dut.go_read_i.eq(0)
+    yield dut.go_rd_i.eq(0)
     yield
-    yield dut.go_write_i.eq(1)
+    yield dut.go_wr_i.eq(1)
     yield
-    yield dut.go_write_i.eq(0)
+    yield dut.go_wr_i.eq(0)
     yield
 
 def test_dcell():

diff --git a/src/scoreboard/ldst_matrix.py b/src/scoreboard/ldst_matrix.py
index b872155d8f05945a49c5aa43238a3507ab129944..dc9d736238a3883301194fbd339b5ba5cb226edc 100644 (file)
--- a/src/scoreboard/ldst_matrix.py
+++ b/src/scoreboard/ldst_matrix.py
@@ -114,13 +114,13 @@ def d_matrix_sim(dut):
     yield
     yield dut.issue_i.eq(0)
     yield
-    yield dut.go_read_i.eq(1)
+    yield dut.go_rd_i.eq(1)
     yield
-    yield dut.go_read_i.eq(0)
+    yield dut.go_rd_i.eq(0)
     yield
-    yield dut.go_write_i.eq(1)
+    yield dut.go_wr_i.eq(1)
     yield
-    yield dut.go_write_i.eq(0)
+    yield dut.go_wr_i.eq(0)
     yield
 
 def test_d_matrix():

diff --git a/src/scoreboard/shadow_fn.py b/src/scoreboard/shadow_fn.py
index a60f9d9541fc95f00648c8efdc73a91d4544a6bd..75f80513a56e305676424fc08471389c17a0f118 100644 (file)
--- a/src/scoreboard/shadow_fn.py
+++ b/src/scoreboard/shadow_fn.py
@@ -56,13 +56,13 @@ def shadow_fn_unit_sim(dut):
     yield
     yield dut.issue_i.eq(0)
     yield
-    yield dut.go_read_i.eq(1)
+    yield dut.go_rd_i.eq(1)
     yield
-    yield dut.go_read_i.eq(0)
+    yield dut.go_rd_i.eq(0)
     yield
-    yield dut.go_write_i.eq(1)
+    yield dut.go_wr_i.eq(1)
     yield
-    yield dut.go_write_i.eq(0)
+    yield dut.go_wr_i.eq(0)
     yield