add a new make target for setting coldboot firmware at 0xfff0_0000

put reset values of pc and msr into Issuer explicitly on reset

diff --git a/Makefile b/Makefile
index f318ae315da4e8b0b21fe6d2ab1f44fdb9817c1a..736cd7b1ac2ace8e379e6a941d3e1f0adaf4c0de 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -69,6 +69,12 @@ microwatt_external_core_spi:
             --pc-reset 0x10000000 \
             external_core_top.v
 
+microwatt_external_core_bram:
+       python3 src/soc/simple/issuer_verilog.py --microwatt-compat \
+            --enable-mmu \
+            --pc-reset 0xFFF00000 \
+            external_core_top.v
+
 # build the litex libresoc SoC without 4k SRAMs
 ls180_verilog_build: ls180_verilog
        make -C soc/soc/litex/florent ls180

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 20a396c39000e52baca7ba47024df045db04262a..9a4abacc3135e647ae4be3d9a8b7882e7ce68fe4 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -159,7 +159,9 @@ class NonProductionCore(ControlBase):
             # urr store I-Cache in core so it is easier to get at
             self.icache = lsi.icache
 
-        # alternative reset values for STATE regs
+        # alternative reset values for STATE regs. these probably shouldn't
+        # be set, here, instead have them done by Issuer. which they are.
+        # as well. because core.state overrides them. sigh.
         self.msr_at_reset = 0x0
         self.pc_at_reset = 0x0
         if hasattr(pspec, "msr_reset") and isinstance(pspec.msr_reset, int):

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 5f556d3e2aa765e413c8396683998079b180e7c1..176264efefed53534f19c0b00bf34d4c6f36ce28 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -615,6 +615,9 @@ class TestIssuerBase(Elaboratable):
         # reset current state if core reset requested
         with m.If(core_rst):
             m.d.sync += self.cur_state.eq(0)
+            # and, sigh, set configured values, which are also done in regfile
+            m.d.sync += self.cur_state.pc.eq(self.core.pc_at_reset)
+            m.d.sync += self.cur_state.msr.eq(self.core.msr_at_reset)
 
         # check halted condition: requested PC to execute matches DMI stop addr
         # and immediately stop. address of 0xffff_ffff_ffff_ffff can never