Replace MSB-i by symbolic subfield indices and selectors

diff --git a/src/soc/consts.py b/src/soc/consts.py
index f86a80d845d94508c9886783dcb3f2eaae485025..72bbe08de4feeeb747910d7f8e3c7c565f452270 100644 (file)
--- a/src/soc/consts.py
+++ b/src/soc/consts.py
@@ -178,3 +178,43 @@ class TT:
     ILLEG = 1<<7 # currently the max
     # TODO: support for TM_BAD_THING (not included yet in trap main_stage.py)
     size = 8 # MUST update this to contain the full number of Trap Types
+
+
+# EXTRA3 3-bit subfield (spec)
+class SPECb:
+    VEC = 0  # 1 for vector, 0 for scalar
+    MSB = 1  # augmented register number, MSB
+    LSB = 2  # augmented register number, LSB
+
+
+SPEC_SIZE = 3
+SPEC = SPECb
+botchify(SPECb, SPEC, SPEC_SIZE-1)
+
+
+# EXTRA field, with EXTRA2 subfield encoding
+class EXTRA2b:
+    IDX0_VEC = 0
+    IDX0_MSB = 1
+    IDX1_VEC = 2
+    IDX1_MSB = 3
+    IDX2_VEC = 4
+    IDX2_MSB = 5
+    IDX3_VEC = 6
+    IDX3_MSB = 7
+    RESERVED = 8
+
+
+EXTRA2_SIZE = 9
+EXTRA2 = EXTRA2b
+botchify(EXTRA2b, EXTRA2, EXTRA2_SIZE-1)
+
+
+# EXTRA field, with EXTRA3 subfield encoding
+class EXTRA3:
+    IDX0 = [0, 1, 2]
+    IDX1 = [3, 4, 5]
+    IDX2 = [6, 7, 8]
+
+
+EXTRA3_SIZE = 9

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index fbfd364043428f95df6a5c20ccd90fc9fa0441d8..63a6a82cbfb5b32f97c5e5525def53eb35d44556 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -27,7 +27,7 @@ from soc.decoder.power_enums import (MicrOp, CryIn, Function,
 from soc.decoder.decode2execute1 import (Decode2ToExecute1Type, Data,
                                          Decode2ToOperand)
 from soc.sv.svp64 import SVP64Rec
-from soc.consts import MSR
+from soc.consts import (MSR, sel, SPEC, EXTRA2, EXTRA3)
 
 from soc.regfile.regfiles import FastRegs
 from soc.consts import TT
@@ -95,6 +95,7 @@ class SVP64ExtraSpec(Elaboratable):
         m = Module()
         comb = m.d.comb
         spec = self.spec
+        extra = self.extra
 
         # back in the LDSTRM-* and RM-* files generated by sv_analysis.py
         # we marked every op with an Etype: EXTRA2 or EXTRA3, and also said
@@ -105,22 +106,26 @@ class SVP64ExtraSpec(Elaboratable):
             with m.Case(SVEtype.EXTRA2):
                 with m.Switch(self.idx):
                     with m.Case(SVEXTRA.Idx0):  # 1st 2 bits [0:1]
-                        comb += spec[1:3].eq(self.extra[8-1:9])
+                        comb += spec[SPEC.VEC].eq(extra[EXTRA2.IDX0_VEC])
+                        comb += spec[SPEC.MSB].eq(extra[EXTRA2.IDX0_MSB])
                     with m.Case(SVEXTRA.Idx1):  # 2nd 2 bits [2:3]
-                        comb += spec[1:3].eq(self.extra[8-3:8-1])
+                        comb += spec[SPEC.VEC].eq(extra[EXTRA2.IDX1_VEC])
+                        comb += spec[SPEC.MSB].eq(extra[EXTRA2.IDX1_MSB])
                     with m.Case(SVEXTRA.Idx2):  # 3rd 2 bits [4:5]
-                        comb += spec[1:3].eq(self.extra[8-5:8-3])
+                        comb += spec[SPEC.VEC].eq(extra[EXTRA2.IDX2_VEC])
+                        comb += spec[SPEC.MSB].eq(extra[EXTRA2.IDX2_MSB])
                     with m.Case(SVEXTRA.Idx3):  # 4th 2 bits [6:7]
-                        comb += spec[1:3].eq(self.extra[8-7:8-5])
+                        comb += spec[SPEC.VEC].eq(extra[EXTRA2.IDX3_VEC])
+                        comb += spec[SPEC.MSB].eq(extra[EXTRA2.IDX3_MSB])
             # 3-bit index selection mode
             with m.Case(SVEtype.EXTRA3):
                 with m.Switch(self.idx):
                     with m.Case(SVEXTRA.Idx0):  # 1st 3 bits [0:2]
-                        comb += spec.eq(self.extra[8-2:9])
+                        comb += spec.eq(sel(extra, EXTRA3.IDX0))
                     with m.Case(SVEXTRA.Idx1):  # 2nd 3 bits [3:5]
-                        comb += spec.eq(self.extra[8-5:8-2])
+                        comb += spec.eq(sel(extra, EXTRA3.IDX1))
                     with m.Case(SVEXTRA.Idx2):  # 3rd 3 bits [6:8]
-                        comb += spec.eq(self.extra[8-8:8-5])
+                        comb += spec.eq(sel(extra, EXTRA3.IDX2))
                     # cannot fit more than 9 bits so there is no 4th thing
 
         return m