missing comb +=

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 44aff9e43e340e5a9e6d4759f66d5fefe72ff9b6..28579a5eb8e1c0010fc078eb8b9ed0cb1e14ee30 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -318,7 +318,7 @@ class RegStage1(RecordObject):
         # Cache hit state
         self.hit_way          = Signal(WAY_BITS)
         self.hit_load_valid   = Signal()
-        self.hit_index        = Signal(NUM_LINES)
+        self.hit_index        = Signal(INDEX_BITS)
         self.cache_hit        = Signal()
 
         # TLB hit state
@@ -852,7 +852,7 @@ class DCache(Elaboratable):
 
         # The way to replace on a miss
         with m.If(r1.write_tag):
-            replace_way.eq(plru_victim[r1.store_index])
+            comb += replace_way.eq(plru_victim[r1.store_index])
         with m.Else():
             comb += replace_way.eq(r1.store_way)