Fix various imports in src/unused/

Fixes: 1abb7996 ("move unused out of soc directory")

diff --git a/src/unused/TLB/PermissionValidator.py b/src/unused/TLB/PermissionValidator.py
index 5bc90b2ff93588dac0cf8c87034ef1aeed8eb35b..19c8618d7d85ee07e891b953a4dcc1fffda50f17 100644 (file)
--- a/src/unused/TLB/PermissionValidator.py
+++ b/src/unused/TLB/PermissionValidator.py
@@ -1,7 +1,7 @@
 from nmigen import Module, Signal, Elaboratable
 from nmigen.cli import main
 
-from soc.TLB.PteEntry import PteEntry
+from unused.TLB.PteEntry import PteEntry
 
 
 class PermissionValidator(Elaboratable):

diff --git a/src/unused/TLB/ariane/test/test_plru.py b/src/unused/TLB/ariane/test/test_plru.py
index 9222d7969e913f2adbaa0104d623b4edf62b23f4..92b4efe0019192ed0799b27cff7e07226a880576 100644 (file)
--- a/src/unused/TLB/ariane/test/test_plru.py
+++ b/src/unused/TLB/ariane/test/test_plru.py
@@ -1,5 +1,5 @@
 import sys
-from soc.TLB.ariane.plru import PLRU
+from unused.TLB.ariane.plru import PLRU
 from nmigen.compat.sim import run_simulation
 
 

diff --git a/src/unused/TLB/ariane/test/test_ptw.py b/src/unused/TLB/ariane/test/test_ptw.py
index 396975664c12069b10284620cc2d401a8c3e456a..0fcd7682b6ce0ca71dc389acc754cbc05e007f80 100644 (file)
--- a/src/unused/TLB/ariane/test/test_ptw.py
+++ b/src/unused/TLB/ariane/test/test_ptw.py
@@ -1,5 +1,5 @@
 from nmigen.compat.sim import run_simulation
-from soc.TLB.ariane.ptw import PTW, PTE
+from unused.TLB.ariane.ptw import PTW, PTE
 
 # unit was changed, test needs to be changed
 

diff --git a/src/unused/TLB/ariane/test/test_tlb.py b/src/unused/TLB/ariane/test/test_tlb.py
index e1b17b8b14a058902eb692f9bc961005eddd96d5..a50eeb6587bbb0e94146505b5a1249489ee301eb 100644 (file)
--- a/src/unused/TLB/ariane/test/test_tlb.py
+++ b/src/unused/TLB/ariane/test/test_tlb.py
@@ -1,6 +1,6 @@
 from nmigen.compat.sim import run_simulation
 
-from soc.TLB.ariane.tlb import TLB
+from unused.TLB.ariane.tlb import TLB
 
 
 def set_vaddr(addr):

diff --git a/src/unused/TLB/ariane/test/test_tlb_content.py b/src/unused/TLB/ariane/test/test_tlb_content.py
index 1bc60d88c3a08b51c59ce5a1ce38563195cd1afe..c16e2c7651ee01cea779065a4b937cc3bdb65588 100644 (file)
--- a/src/unused/TLB/ariane/test/test_tlb_content.py
+++ b/src/unused/TLB/ariane/test/test_tlb_content.py
@@ -1,6 +1,6 @@
 from nmigen.compat.sim import run_simulation
 
-from soc.TLB.ariane.tlb_content import TLBContent
+from unused.TLB.ariane.tlb_content import TLBContent
 from soc.TestUtil.test_helper import assert_op, assert_eq
 
 

diff --git a/src/unused/TLB/ariane/tlb.py b/src/unused/TLB/ariane/tlb.py
index 72b67a2dcc56aa76aca561f5da3345a99c36c2ab..c16840bb296aeb3001dbcda68af7d54c049fc615 100644 (file)
--- a/src/unused/TLB/ariane/tlb.py
+++ b/src/unused/TLB/ariane/tlb.py
@@ -29,9 +29,9 @@ from nmigen import Signal, Module, Cat, Const, Array, Elaboratable
 from nmigen.cli import verilog, rtlil
 from nmigen.lib.coding import Encoder
 
-from soc.TLB.ariane.ptw import TLBUpdate, PTE, ASID_WIDTH
-from soc.TLB.ariane.plru import PLRU
-from soc.TLB.ariane.tlb_content import TLBContent
+from unused.TLB.ariane.ptw import TLBUpdate, PTE, ASID_WIDTH
+from unused.TLB.ariane.plru import PLRU
+from unused.TLB.ariane.tlb_content import TLBContent
 
 TLB_ENTRIES = 8
 

diff --git a/src/unused/TLB/ariane/tlb_content.py b/src/unused/TLB/ariane/tlb_content.py
index bfd17c13bbcb5802cf20cd73dc30de879e54e49a..84ba219b7d3d49b896916809cec4aca1a169a720 100644 (file)
--- a/src/unused/TLB/ariane/tlb_content.py
+++ b/src/unused/TLB/ariane/tlb_content.py
@@ -1,6 +1,6 @@
 from nmigen import Signal, Module, Cat, Const, Elaboratable
 
-from soc.TLB.ariane.ptw import TLBUpdate, PTE
+from unused.TLB.ariane.ptw import TLBUpdate, PTE
 
 
 class TLBEntry:

diff --git a/src/unused/TLB/test/test_LFSR2.py b/src/unused/TLB/test/test_LFSR2.py
index 33208f831b0c69456818f5d4356f1e74008afd23..cd74c4623c9f949299ef7253ba86285a13687329 100644 (file)
--- a/src/unused/TLB/test/test_LFSR2.py
+++ b/src/unused/TLB/test/test_LFSR2.py
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: LGPL-2.1-or-later
 # See Notices.txt for copyright information
-from soc.TLB.LFSR import LFSR, LFSRPolynomial, LFSR_POLY_3
+from unused.TLB.LFSR import LFSR, LFSRPolynomial, LFSR_POLY_3
 
 from nmigen.back.pysim import Simulator, Delay, Tick
 import unittest

diff --git a/src/unused/TLB/test/test_address_encoder.py b/src/unused/TLB/test/test_address_encoder.py
index 70d435d6de51565af74ca39095adee26e3c68acc..72880dd9b7e7e7b60e70c9a37c6d6b8d995b32f1 100644 (file)
--- a/src/unused/TLB/test/test_address_encoder.py
+++ b/src/unused/TLB/test/test_address_encoder.py
@@ -1,5 +1,5 @@
 from nmigen.compat.sim import run_simulation
-from soc.TLB.AddressEncoder import AddressEncoder
+from unused.TLB.AddressEncoder import AddressEncoder
 from soc.TestUtil.test_helper import assert_eq, assert_ne, assert_op
 
 

diff --git a/src/unused/TLB/test/test_cam.py b/src/unused/TLB/test/test_cam.py
index d11cd974f58187669b0c5401c2f15ca9ba1c8a78..a038168364aad3c42ca4302edb381806cf99f4cc 100644 (file)
--- a/src/unused/TLB/test/test_cam.py
+++ b/src/unused/TLB/test/test_cam.py
@@ -1,6 +1,6 @@
 from nmigen.compat.sim import run_simulation
 
-from soc.TLB.Cam import Cam
+from unused.TLB.Cam import Cam
 
 from soc.TestUtil.test_helper import assert_eq, assert_ne, assert_op
 

diff --git a/src/unused/TLB/test/test_cam_entry.py b/src/unused/TLB/test/test_cam_entry.py
index 961445b69d3261b1159e2aafef244241b7d2019f..80901ca554e4b9eb1d96d291d3ffd025174ac134 100644 (file)
--- a/src/unused/TLB/test/test_cam_entry.py
+++ b/src/unused/TLB/test/test_cam_entry.py
@@ -1,7 +1,7 @@
 from nmigen.compat.sim import run_simulation
 
 from soc.TestUtil.test_helper import assert_eq, assert_ne, assert_op
-from soc.TLB.CamEntry import CamEntry
+from unused.TLB.CamEntry import CamEntry
 
 # This function allows for the easy setting of values to the Cam Entry
 # Arguments:

diff --git a/src/unused/TLB/test/test_permission_validator.py b/src/unused/TLB/test/test_permission_validator.py
index b52b5459244a834bc3d926246fdbca849af8b3e3..94e99c10a7bd68222dfbdd9136423ba6eaf375b8 100644 (file)
--- a/src/unused/TLB/test/test_permission_validator.py
+++ b/src/unused/TLB/test/test_permission_validator.py
@@ -1,6 +1,6 @@
 from nmigen.compat.sim import run_simulation
 
-from soc.TLB.PermissionValidator import PermissionValidator
+from unused.TLB.PermissionValidator import PermissionValidator
 
 from soc.TestUtil.test_helper import assert_op
 

diff --git a/src/unused/TLB/test/test_pte_entry.py b/src/unused/TLB/test/test_pte_entry.py
index 51b3dcf012d1fed4791bfb0b0fbbdb02ba5c0149..390a94ecd1ad4e6516fe1c21b4061736af04bbbe 100644 (file)
--- a/src/unused/TLB/test/test_pte_entry.py
+++ b/src/unused/TLB/test/test_pte_entry.py
@@ -1,6 +1,6 @@
 from nmigen.compat.sim import run_simulation
 
-from soc.TLB.PteEntry import PteEntry
+from unused.TLB.PteEntry import PteEntry
 
 from soc.TestUtil.test_helper import assert_op
 

diff --git a/src/unused/TLB/test/test_set_associative_cache.py b/src/unused/TLB/test/test_set_associative_cache.py
index edec055b3545943f2c8c3e8b5399989af99544d6..9b48bb033bdce9d0641839e778e5bae080a0fe89 100644 (file)
--- a/src/unused/TLB/test/test_set_associative_cache.py
+++ b/src/unused/TLB/test/test_set_associative_cache.py
@@ -1,6 +1,6 @@
 from nmigen.compat.sim import run_simulation
 
-from soc.TLB.SetAssociativeCache import SetAssociativeCache
+from unused.TLB.SetAssociativeCache import SetAssociativeCache
 
 from soc.TestUtil.test_helper import assert_eq, assert_ne, assert_op
 

diff --git a/src/unused/TLB/test/test_tlb.py b/src/unused/TLB/test/test_tlb.py
index 38656623effd02bdc4b360d0c82c9e96f153e607..e925c62d79cdf0548f1fef0e17d5775f1758d221 100644 (file)
--- a/src/unused/TLB/test/test_tlb.py
+++ b/src/unused/TLB/test/test_tlb.py
@@ -3,7 +3,7 @@
 
 from nmigen.compat.sim import run_simulation
 
-from soc.TLB.TLB import TLB
+from unused.TLB.TLB import TLB
 
 from soc.TestUtil.test_helper import assert_op, assert_eq
 

diff --git a/src/unused/iommu/axi_rab/test/test_ram_tp_no_change.py b/src/unused/iommu/axi_rab/test/test_ram_tp_no_change.py
index 8d23ef05375713cb99571e4743e2239f10384320..161daa1b3aeeffdb1ea91e4510c34bb37af0b7cc 100644 (file)
--- a/src/unused/iommu/axi_rab/test/test_ram_tp_no_change.py
+++ b/src/unused/iommu/axi_rab/test/test_ram_tp_no_change.py
@@ -1,4 +1,4 @@
-from ram_tp_write_first import ram_tp_write_first
+from ..ram_tp_write_first import ram_tp_write_first
 from nmigen.compat.sim import run_simulation
 import sys
 sys.path.append("../")

diff --git a/src/unused/iommu/axi_rab/test/test_slice_top.py b/src/unused/iommu/axi_rab/test/test_slice_top.py
index c234b9080dff8a5f599f396947f3f1674860cc74..50f3321e13cc73c5ec10e63533e3611b34ba26f3 100644 (file)
--- a/src/unused/iommu/axi_rab/test/test_slice_top.py
+++ b/src/unused/iommu/axi_rab/test/test_slice_top.py
@@ -2,7 +2,7 @@ from nmigen.compat.sim import run_simulation
 import sys
 sys.path.append("../")
 # sys.path.append("../../../TestUtil")
-from slice_top import slice_top
+from ..slice_top import slice_top
 
 def tbench(dut):
     yield

diff --git a/src/unused/simulator/test_sim.py b/src/unused/simulator/test_sim.py
index 0a26380cd996d20f4bd65585bc1bbcea257bd5bc..3b25499750916ab0716484da18c8afc48e025eaf 100644 (file)
--- a/src/unused/simulator/test_sim.py
+++ b/src/unused/simulator/test_sim.py
@@ -2,7 +2,7 @@ from nmigen import Module, Signal
 from nmigen.back.pysim import Simulator, Delay
 from nmigen.test.utils import FHDLTestCase
 import unittest
-from soc.simulator.internalop_sim import InternalOpSimulator
+from unused.simulator.internalop_sim import InternalOpSimulator
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_enums import (Function, InternalOp,
                                      In1Sel, In2Sel, In3Sel,