Get build starting

diff --git a/nix/verilog.nix b/nix/verilog.nix
index 55755343cb3b021b34c3a8435f31c94dfd3181c3..cb6df044788efbae3c918bc48dc74eb1bd18b648 100644 (file)
--- a/nix/verilog.nix
+++ b/nix/verilog.nix
@@ -10,13 +10,15 @@ stdenv.mkDerivation {
 
   strictDeps = true;
 
-  nativeBuildInputs = with python3Packages; [ python libresoc-ieee754fpu libresoc-openpower-isa ];
+  nativeBuildInputs = with python3Packages; [ nmigen-soc python libresoc-ieee754fpu libresoc-openpower-isa ];
 
   configurePhase = "true";
 
   buildPhase = ''
     runHook preBuild
-    python3 src/soc/simple/issuer_verilog.py \
+    cd src
+    export PYTHONPATH="$PWD:$PYTHONPATH"
+    python3 soc/simple/issuer_verilog.py \
       --debug=jtag --enable-core --enable-pll \
       --enable-xics --enable-sram4x4kblock --disable-svp64 \
       libresoc.v