split out Decode2ToExecuteType fields involving registers

into constants Decode2ToOperand

diff --git a/src/soc/decoder/decode2execute1.py b/src/soc/decoder/decode2execute1.py
index df98c0f4aa0ac7a49648fdcd17626dc1a565eaf9..5ca2d2693ea97e0b2928fb4e1076b75e3f9609ed 100644 (file)
--- a/src/soc/decoder/decode2execute1.py
+++ b/src/soc/decoder/decode2execute1.py
@@ -23,14 +23,45 @@ class Data(Record):
         return [self.data, self.ok]
 
 
-class Decode2ToExecute1Type(RecordObject):
+class Decode2ToOperand(RecordObject):
 
-    def __init__(self, name=None, asmcode=True):
+    def __init__(self, name=None):
 
         RecordObject.__init__(self, name=name)
 
         self.insn_type = Signal(InternalOp, reset_less=True)
         self.fn_unit = Signal(Function, reset_less=True)
+        self.imm_data = Data(64, name="imm")
+
+        self.lk = Signal(reset_less=True)
+        self.rc = Data(1, "rc")
+        self.oe = Data(1, "oe")
+        self.xer_in = Signal(reset_less=True)   # xer might be read
+        self.xer_out = Signal(reset_less=True)  # xer might be written
+        self.invert_a = Signal(reset_less=True)
+        self.zero_a = Signal(reset_less=True)
+        self.input_carry = Signal(CryIn, reset_less=True)
+        self.output_carry = Signal(reset_less=True)
+        self.input_cr = Signal(reset_less=True)  # instr. has a CR as input
+        self.output_cr = Signal(reset_less=True) # instr. has a CR as output
+        self.invert_out = Signal(reset_less=True)
+        self.is_32bit = Signal(reset_less=True)
+        self.is_signed = Signal(reset_less=True)
+        self.insn = Signal(32, reset_less=True)
+        self.data_len = Signal(4, reset_less=True) # bytes
+        self.byte_reverse  = Signal(reset_less=True)
+        self.sign_extend  = Signal(reset_less=True)# do we need this?
+        self.update  = Signal(reset_less=True) # LD/ST is "update" variant
+        self.traptype  = Signal(5, reset_less=True) # see trap main_stage.py
+        self.trapaddr  = Signal(13, reset_less=True)
+
+
+class Decode2ToExecute1Type(Decode2ToOperand):
+
+    def __init__(self, name=None, asmcode=True):
+
+        Decode2ToOperand.__init__(self, name=name)
+
         if asmcode:
             self.asmcode = Signal(8, reset_less=True) # only for simulator
         self.nia = Signal(64, reset_less=True)
@@ -39,7 +70,6 @@ class Decode2ToExecute1Type(RecordObject):
         self.read_reg1 = Data(5, name="reg1")
         self.read_reg2 = Data(5, name="reg2")
         self.read_reg3 = Data(5, name="reg3")
-        self.imm_data = Data(64, name="imm")
         self.write_spr = Data(SPR, name="spro")
         self.read_spr1 = Data(SPR, name="spr1")
         #self.read_spr2 = Data(SPR, name="spr2")
@@ -55,25 +85,4 @@ class Decode2ToExecute1Type(RecordObject):
         self.read_cr_whole = Signal(reset_less=True)
         self.write_cr = Data(3, name="cr_out")
         self.write_cr_whole = Signal(reset_less=True)
-        self.lk = Signal(reset_less=True)
-        self.rc = Data(1, "rc")
-        self.oe = Data(1, "oe")
-        self.xer_in = Signal(reset_less=True)   # xer might be read
-        self.xer_out = Signal(reset_less=True)  # xer might be written
-        self.invert_a = Signal(reset_less=True)
-        self.zero_a = Signal(reset_less=True)
-        self.invert_out = Signal(reset_less=True)
-        self.input_carry = Signal(CryIn, reset_less=True)
-        self.output_carry = Signal(reset_less=True)
-        self.input_cr = Signal(reset_less=True)  # instr. has a CR as input
-        self.output_cr = Signal(reset_less=True) # instr. has a CR as output
-        self.is_32bit = Signal(reset_less=True)
-        self.is_signed = Signal(reset_less=True)
-        self.insn = Signal(32, reset_less=True)
-        self.data_len = Signal(4, reset_less=True) # bytes
-        self.byte_reverse  = Signal(reset_less=True)
-        self.sign_extend  = Signal(reset_less=True)# do we need this?
-        self.update  = Signal(reset_less=True) # LD/ST is "update" variant
-        self.traptype  = Signal(5, reset_less=True) # see trap main_stage.py
-        self.trapaddr  = Signal(13, reset_less=True)