only add clock-settings on ECP5 due to special SPI clock handling

(Tercel QSPI)

diff --git a/src/soc/bus/tercel.py b/src/soc/bus/tercel.py
index f04f356aa6ced45993ac5fd0cd7684d74b49e5ea..54ba9252fb7eeeb49496531c2098101b8210955c 100644 (file)
--- a/src/soc/bus/tercel.py
+++ b/src/soc/bus/tercel.py
@@ -170,9 +170,11 @@ class Tercel(Elaboratable):
                 pad = getattr(pins, "dq%d" % i)
                 comb += pad.o.eq(self.dq_out[i])
                 comb += pad.oe.eq(self.dq_direction[i])
-                comb += pad.o_clk.eq(ClockSignal())
                 comb += self.dq_in[i].eq(pad.i)
-                comb += pad.i_clk.eq(ClockSignal())
+                # ECP5 needs special handling for the SPI clock, sigh.
+                if self.lattice_ecp5_usrmclk:
+                    comb += pad.o_clk.eq(ClockSignal())
+                    comb += pad.i_clk.eq(ClockSignal())
             # XXX invert handled by SPIFlashResource
             comb += pins.cs_n.eq(self.cs_n_out)
             # ECP5 needs special handling for the SPI clock, sigh.