- self.wr_addr_i = Signal(addr_width)
- """write port address"""
- self.wr_data_i = Signal(data_width)
- """write port data"""
- self.wr_we_i = Signal(we_width)
- """write port enable"""
- self.rd_addr_i = Signal(addr_width)
- """read port address"""
- self.rd_data_o = Signal(data_width)
- """read port data"""
- self.phase = Signal()
- """even/odd cycle indicator"""
- self.dbg_a = Signal(addr_width)
- """debug read port address"""
- self.dbg_q1 = Signal(data_width)
- """debug read port data (first memory)"""
- self.dbg_q2 = Signal(data_width)
- """debug read port data (second memory)"""
+ self.wr_addr_i = Signal(addr_width); """write port address"""
+ self.wr_data_i = Signal(data_width); """write port data"""
+ self.wr_we_i = Signal(we_width); """write port enable"""
+ self.rd_addr_i = Signal(addr_width); """read port address"""
+ self.rd_data_o = Signal(data_width); """read port data"""
+ self.phase = Signal(); """even/odd cycle indicator"""
+ self.dbg_a = Signal(addr_width); """debug read port address"""
+ self.dbg_q1 = Signal(data_width); """debug read port data (1st mem)"""
+ self.dbg_q2 = Signal(data_width); """debug read port data (2nd mem)"""