fix issue with priv_mode not being passed correctly to MMU

on instruction load

diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py
index 081ff0194685169f14f5226a56a87f839a42bcd3..6283f8ac439824002f55b29ba0803bb363133572 100644 (file)
--- a/src/soc/fu/ldst/loadstore.py
+++ b/src/soc/fu/ldst/loadstore.py
@@ -123,6 +123,7 @@ class LoadStore1(PortInterfaceBase):
         self.state         = Signal(State)
         self.instr_fault   = Signal()  # indicator to request i-cache MMU lookup
         self.r_instr_fault  = Signal() # accessed in external_busy
+        self.priv_mode     = Signal() # only for instruction fetch (not LDST)
         self.align_intr    = Signal()
         self.busy          = Signal()
         self.wait_dcache   = Signal()
@@ -445,8 +446,10 @@ class LoadStore1(PortInterfaceBase):
         m.d.comb += m_out.valid.eq(mmureq)
         m.d.comb += m_out.iside.eq(self.instr_fault)
         m.d.comb += m_out.load.eq(ldst_r.load)
-        m.d.comb += m_out.priv.eq(ldst_r.priv_mode)
-        # m_out.priv <= r.priv_mode; TODO
+        with m.If(self.instr_fault):
+            m.d.comb += m_out.priv.eq(self.priv_mode)
+        with m.Else():
+            m.d.comb += m_out.priv.eq(ldst_r.priv_mode)
         m.d.comb += m_out.tlbie.eq(self.tlbie)
         # m_out.mtspr <= mmu_mtspr; # TODO
         # m_out.sprn <= sprn; # TODO

diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py
index c1d4d74f9113f19b02ecf4d43395a9f738d36087..24be3f5402710bed1fb3a016e672ef12cc13671b 100644 (file)
--- a/src/soc/fu/mmu/fsm.py
+++ b/src/soc/fu/mmu/fsm.py
@@ -225,6 +225,7 @@ class FSMMMUStage(ControlBase):
                     # from accepting any other LD/ST requests.
                     comb += valid.eq(1)   # start "pulse"
                     comb += ldst.instr_fault.eq(blip)
+                    comb += ldst.priv_mode.eq(~msr_i[MSR.PR])
                     comb += ldst.maddr.eq(cia_i)
                     # XXX should not access this!
                     comb += done.eq(ldst.done)