bit of munging of Makefile, new targets
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 30 Mar 2021 10:38:44 +0000 (11:38 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 30 Mar 2021 10:38:44 +0000 (11:38 +0100)
Makefile

index 25b6135237a37318dbe5e80290633ecdbe2d705c..b7d73ee58c280d298136d9773db7bffa972747c9 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -11,7 +11,7 @@ mkpinmux:
        cp pinmux/ls180/ls180_pins.py src/soc/debug
        cp pinmux/ls180/ls180_pins.py src/soc/litex/florent/libresoc
 
-install: develop mkpinmux
+install: gitupdate develop mkpinmux svanalysis
 
 pywriter:
        python3 src/soc/decoder/pseudo/pywriter.py
@@ -21,13 +21,14 @@ svanalysis:
 
 develop:
        python3 setup.py develop # yes, develop, not install
-       python3 src/soc/decoder/pseudo/pywriter.py
 
+# build and run libresoc litex simulation
 run_sim:
-       python3 src/soc/simple/issuer_verilog.py --disable-svp64\
+       python3 src/soc/simple/issuer_verilog.py --disable-svp64 \
                        src/soc/litex/florent/libresoc/libresoc.v
        python3 src/soc/litex/florent/sim.py --cpu=libresoc
 
+# and with test gpio (useful for XICS IRC testing)
 testgpio_run_sim:
        python3 src/soc/simple/issuer_verilog.py \
                        src/soc/litex/florent/libresoc/libresoc.v \
@@ -36,11 +37,26 @@ testgpio_run_sim:
                        --variant=standardjtagtestgpio
 
 ls180_verilog:
+       python3 src/soc/simple/issuer_verilog.py \
+               --debug=jtag --enable-core --enable-pll \
+               --enable-xics --disable-svp64 \
+                       src/soc/litex/florent/libresoc/libresoc.v
+
+ls180_4k_verilog:
        python3 src/soc/simple/issuer_verilog.py \
                --debug=jtag --enable-core --enable-pll \
                --enable-xics --enable-sram4x4kblock --disable-svp64 \
                        src/soc/litex/florent/libresoc/libresoc.v
 
+# build the litex libresoc SoC without 4k SRAMs
+ls180_4ksram_verilog_build: ls180_verilog
+       make -C soc/soc/litex/florent ls1804k
+
+# build the litex libresoc SoC with 4k SRAMs
+ls180_4ksram_verilog_build: ls180_4k_verilog
+       make -C soc/soc/litex/florent ls1804k
+
+# testing (usually done at install time)
 test: install
        python3 setup.py test # could just run nosetest3...
 
@@ -58,13 +74,16 @@ BUILDDIR      = build
 help:
        @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
 
+# copies all documentation to libre-soc (libre-soc admins only)
+htmlupload: clean html
+       rsync -HPavz --delete build/html/* \
+        libre-soc.org:/var/www/libre-soc.org/docs/soc/
+
 # Catch-all target: route all unknown targets to Sphinx using the new
 # "make mode" option.  $(O) is meant as a shortcut for $(SPHINXOPTS).
 %: Makefile
+       echo "catch-all falling through to sphinx for document building"
        mkdir -p "$(SOURCEDIR)"/src/gen
        sphinx-apidoc --ext-autodoc -o "$(SOURCEDIR)"/src/gen ./src/soc
        @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
 
-htmlupload: clean html
-       rsync -HPavz --delete build/html/* \
-        libre-soc.org:/var/www/libre-soc.org/docs/soc/