add missing module

diff --git a/src/soc/fu/div/pipeline.py b/src/soc/fu/div/pipeline.py
index 7fbbf10cfd812330d8db43ed975086aef680fb65..6fc01a50c715944974cb7e64aad790f34aada01d 100644 (file)
--- a/src/soc/fu/div/pipeline.py
+++ b/src/soc/fu/div/pipeline.py
@@ -84,5 +84,6 @@ class DivBasePipe(ControlBase):
             name = f"pipe_middle_{i}"
             setattr(m.submodules, name, self.pipe_middles[i])
         m.submodules.pipe_end = self.pipe_end
+        m.submodules.pipe_final = self.pipe_final
         m.d.comb += self._eqs
         return m