Subsignal("rx", Pins("M1"), IOStandard("LVCMOS33"))
),
- ("spi", 0,
+ ("spi_master", 0,
Subsignal("clk", Pins("J1")),
Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")),
Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")),
]
+pinsin = []
+pinsout = []
for i in range(8):
- _io.append( ("gpio_in", i, Pins("X%d" % i), IOStandard("LVCMOS33")) )
- _io.append( ("gpio_out", i, Pins("Y%d" % i), IOStandard("LVCMOS33")) )
+ pinsin.append("X%d" % i)
+ pinsout.append("Y%d" % i)
+pinsin = ' '.join(pinsin)
+pinsout = ' '.join(pinsout)
+
+_io.append( ("gpio_in", 8, Pins(pinsin), IOStandard("LVCMOS33")) )
+_io.append( ("gpio_out", 8, Pins(pinsout), IOStandard("LVCMOS33")) )
# Platform -----------------------------------------------------------------------------------------
from litedram.phy.model import SDRAMPHYModel
from litedram.phy.gensdrphy import GENSDRPHY, HalfRateGENSDRPHY
+from litex.soc.cores.gpio import GPIOInOut, GPIOIn, GPIOOut
+from litex.soc.cores.spi import SPIMaster
+
from litex.tools.litex_sim import sdram_module_nphases, get_sdram_phy_settings
from litex.tools.litex_sim import Platform
from libresoc.ls180 import LS180Platform
+from migen import Module
+from litex.soc.interconnect.csr import AutoCSR
+
from libresoc import LibreSoC
from microwatt import Microwatt
from litex.soc.integration.soc import SoCCSRHandler
SoCCSRHandler.supported_address_width.append(12)
+# LiteScope IO -------------------------------------------------
+
+class SoCGPIO(Module, AutoCSR):
+ def __init__(self, in_pads, out_pads):
+ self.input = Signal(len(in_pads))
+ self.output = Signal(len(out_pads))
+
+ # # #
+
+ self.submodules.gpio = GPIOInOut(self.input, self.output)
+
+ def get_csrs(self):
+ return self.gpio.get_csrs()
+
+
# LibreSoCSim -----------------------------------------------------------------
class LibreSoCSim(SoCCore):
platform='sim',
):
assert cpu in ["libresoc", "microwatt"]
- sys_clk_freq = int(100e6)
+ sys_clk_freq = int(50e6)
if platform == 'sim':
platform = Platform()
# "hello_world/hello_world.bin"
# reserve XICS ICP and XICS memory addresses.
- self.mem_map['icp'] = 0xc0004000
- self.mem_map['ics'] = 0xc0005000
- self.mem_map['gpio'] = 0xc0007000
+ self.mem_map['icp'] = 0xc0010000
+ self.mem_map['ics'] = 0xc0011000
+ self.mem_map['gpio'] = 0xc0012000
#self.csr_map["icp"] = 8 # 8 x 0x800 == 0x4000
#self.csr_map["ics"] = 10 # 10 x 0x800 == 0x5000
cpu_cls = LibreSoC if cpu == "libresoc" \
else Microwatt,
#bus_data_width = 64,
- csr_address_width = 12, # limit to 0x4000
+ csr_address_width = 14, # limit to 0x8000
cpu_variant = variant,
csr_data_width = 8,
l2_size = 0,
self.add_constant("MEMTEST_ADDR_DEBUG", 1)
self.add_constant("MEMTEST_DATA_DEBUG", 1)
+ # GPIOs
+ #platform.add_extension([("gpio_in", 0, Pins(8))])
+ self.submodules.gpio_in = GPIOIn(platform.request("gpio_in"))
+ self.add_csr("gpio_in")
+ self.submodules.gpio_out = GPIOIn(platform.request("gpio_out"))
+ self.add_csr("gpio_out")
+
+ # SPI Master
+ self.submodules.spi_master = SPIMaster(
+ pads = platform.request("spi_master"),
+ data_width = 8,
+ sys_clk_freq = sys_clk_freq,
+ spi_clk_freq = 8e6,
+ )
+ self.add_csr("spi_master")
+
# Debug ---------------------------------------------------------------
if not debug:
if args.platform == 'ls180':
soc = LibreSoCSim(cpu=args.cpu, debug=args.debug,
platform=args.platform)
- #soc.add_sdcard()
+ soc.add_sdcard()
+ soc.add_spi_sdcard()
builder = Builder(soc, compile_gateware = True)
builder.build(run = True)
os.chdir("../")