Remove unneeded condition register decoder

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index ec5228695101afd877c2328f18956c6ce0a47ce7..08c9f44d52026e304f38d8387e30eff9068aa46c 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -229,28 +229,6 @@ class DecodeRC(Elaboratable):
 
         return m
 
-class DecodeCR(Elaboratable):
-    """DecodeRc from instruction
-
-    decodes Record bit Rc
-    """
-    def __init__(self, dec):
-        self.dec = dec
-        self.cr_out = Data(3, "cr")
-        self.insn_in = Signal(32, reset_less=True)
-        self.sel_in = Signal(1, reset_less=True)
-
-    def elaborate(self, platform):
-        m = Module()
-        comb = m.d.comb
-
-        # select Record bit out field
-        with m.If(self.sel_in):
-            comb += self.cr_out.data.eq(self.dec.BF[0:-1])
-
-        comb += self.cr_out.ok.eq(self.sel_in)
-        return m
-
 
 class DecodeOE(Elaboratable):
     """DecodeOE from instruction
@@ -309,7 +287,6 @@ class Decode2ToExecute1Type:
         self.write_spr = Data(10, name="spro")
         self.read_spr1 = Data(10, name="spr1")
         self.read_spr2 = Data(10, name="spr2")
-        self.cr_sel    = Data(3, name="cr_sel")
         #self.read_data1 = Signal(64, reset_less=True)
         #self.read_data2 = Signal(64, reset_less=True)
         #self.read_data3 = Signal(64, reset_less=True)
@@ -378,12 +355,11 @@ class PowerDecode2(Elaboratable):
         m.submodules.dec_o = dec_o = DecodeOut(self.dec)
         m.submodules.dec_rc = dec_rc = DecodeRC(self.dec)
         m.submodules.dec_oe = dec_oe = DecodeOE(self.dec)
-        m.submodules.dec_cr = dec_cr = DecodeCR(self.dec)
 
         # copy instruction through...
         for i in [self.e.insn, dec_a.insn_in, dec_b.insn_in,
                   dec_c.insn_in, dec_o.insn_in, dec_rc.insn_in,
-                  dec_oe.insn_in, dec_cr.insn_in]:
+                  dec_oe.insn_in]:
             comb += i.eq(self.dec.opcode_in)
 
         # ...and subdecoders' input fields
@@ -393,7 +369,6 @@ class PowerDecode2(Elaboratable):
         comb += dec_o.sel_in.eq(self.dec.op.out_sel)
         comb += dec_rc.sel_in.eq(self.dec.op.rc_sel)
         comb += dec_oe.sel_in.eq(self.dec.op.rc_sel) # XXX should be OE sel
-        comb += dec_cr.sel_in.eq(self.dec.op.cr_out)
 
         # decode LD/ST length
         with m.Switch(self.dec.op.ldst_len):
@@ -445,7 +420,6 @@ class PowerDecode2(Elaboratable):
         comb += self.e.input_cr.eq(self.dec.op.cr_in)
         comb += self.e.output_cr.eq(self.dec.op.cr_out)
 
-        comb += self.e.cr_sel.eq(dec_cr.cr_out)
 
         return m
 

diff --git a/src/soc/decoder/test/test_decoder_gas.py b/src/soc/decoder/test/test_decoder_gas.py
index dab83c708875db544a2d8678342d5d4d6373ec69..9a09f184da21ed79f1b1065bdc803ce7e44c9c69 100644 (file)
--- a/src/soc/decoder/test/test_decoder_gas.py
+++ b/src/soc/decoder/test/test_decoder_gas.py
@@ -198,7 +198,7 @@ class CmpRegOp:
     def check_results(self, pdecode2):
         r1sel = yield pdecode2.e.read_reg1.data
         r2sel = yield pdecode2.e.read_reg2.data
-        crsel = yield pdecode2.e.cr_sel.data
+        crsel = yield pdecode2.dec.BF[0:-1]
 
         assert(r1sel == self.r1.num)
         assert(r2sel == self.r2.num)