set parent pspec to class with XLEN = 64

diff --git a/src/soc/fu/div/test/helper.py b/src/soc/fu/div/test/helper.py
index 18175f12ffa17819cf4b26318fb2badf0700d6f7..3a854975b1aa2b4999fcdd2ee6c3789a96c38847 100644 (file)
--- a/src/soc/fu/div/test/helper.py
+++ b/src/soc/fu/div/test/helper.py
@@ -163,8 +163,11 @@ class DivTestHelper(unittest.TestCase):
 
         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 
+        class PPspec:
+            XLEN = 64
+        pps = PPspec()
         pspec = DivPipeSpec(
-            id_wid=2, div_pipe_kind=div_pipe_kind, parent_pspec=None)
+            id_wid=2, div_pipe_kind=div_pipe_kind, parent_pspec=pps)
         m.submodules.alu = alu = DivBasePipe(pspec)
 
         comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)

diff --git a/src/soc/fu/div/test/test_pipe_ilang.py b/src/soc/fu/div/test/test_pipe_ilang.py
index a9f0cb27cfe7cf091fb4410d8efeb85937af8519..215b3a65d7e54b48e21c66bf33e36fb15b3f246a 100644 (file)
--- a/src/soc/fu/div/test/test_pipe_ilang.py
+++ b/src/soc/fu/div/test/test_pipe_ilang.py
@@ -6,8 +6,11 @@ from soc.fu.div.pipeline import DivBasePipe
 
 class TestPipeIlang(unittest.TestCase):
     def write_ilang(self, div_pipe_kind):
+        class PPspec:
+            XLEN = 64
+        pps = PPspec()
         pspec = DivPipeSpec(
-            id_wid=2, div_pipe_kind=div_pipe_kind, parent_pspec=None)
+            id_wid=2, div_pipe_kind=div_pipe_kind, parent_pspec=pps)
         alu = DivBasePipe(pspec)
         vl = rtlil.convert(alu, ports=alu.ports())
         with open(f"div_pipeline_{div_pipe_kind.name}.il", "w") as f:

diff --git a/src/soc/fu/mul/test/helper.py b/src/soc/fu/mul/test/helper.py
index 4528f408b96ed5974d3d3788087a893375d8161b..30cb94966d3292916d94b7e809ad70f88e55e609 100644 (file)
--- a/src/soc/fu/mul/test/helper.py
+++ b/src/soc/fu/mul/test/helper.py
@@ -146,7 +146,10 @@ class MulTestHelper(unittest.TestCase):
         m.submodules.pdecode2 = pdecode2 = PowerDecode2(None, opkls, fn_name)
         pdecode = pdecode2.dec
 
-        pspec = MulPipeSpec(id_wid=2, parent_pspec=None)
+        class PPspec:
+            XLEN = 64
+        pps = PPspec()
+        pspec = MulPipeSpec(id_wid=2, parent_pspec=pps)
         m.submodules.alu = alu = MulBasePipe(pspec)
 
         comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)

diff --git a/src/soc/fu/mul/test/test_pipe_ilang.py b/src/soc/fu/mul/test/test_pipe_ilang.py
index c6ffabebffef42d195635bc8f9b3eb190231b64f..7411b586b7ad8c5481c41bc27b4b2cf78ab155cf 100644 (file)
--- a/src/soc/fu/mul/test/test_pipe_ilang.py
+++ b/src/soc/fu/mul/test/test_pipe_ilang.py
@@ -6,7 +6,10 @@ from soc.fu.mul.pipeline import MulBasePipe
 
 class TestPipeIlang(unittest.TestCase):
     def write_ilang(self):
-        pspec = MulPipeSpec(id_wid=2, parent_pspec=None)
+        class PPspec:
+            XLEN = 64
+        pps = PPspec()
+        pspec = MulPipeSpec(id_wid=2, parent_pspec=pps)
         alu = MulBasePipe(pspec)
         vl = rtlil.convert(alu, ports=alu.ports())
         with open("mul_pipeline.il", "w") as f: