Disallow dm=xx on single predication

Adjust test cases accordingly.

diff --git a/src/soc/decoder/isa/test_caller_svp64_predication.py b/src/soc/decoder/isa/test_caller_svp64_predication.py
index 46486c2ecf9865966741f9e72fc449def16a624f..74255c6812dc382d0b0e663f106f5d7ed044674e 100644 (file)
--- a/src/soc/decoder/isa/test_caller_svp64_predication.py
+++ b/src/soc/decoder/isa/test_caller_svp64_predication.py
@@ -120,7 +120,7 @@ class DecoderTestCase(FHDLTestCase):
         # adds, integer predicated mask r3=0b10
         #       1 = 5 + 9   => not to be touched (skipped)
         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
-        isa = SVP64Asm(['sv.add/dm=r3 1.v, 5.v, 9.v'
+        isa = SVP64Asm(['sv.add/m=r3 1.v, 5.v, 9.v'
                        ])
         lst = list(isa)
         print ("listing", lst)
@@ -151,7 +151,7 @@ class DecoderTestCase(FHDLTestCase):
         # adds, CR predicated mask CR4.eq = 1, CR5.eq = 0, invert (ne)
         #       1 = 5 + 9   => not to be touched (skipped)
         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
-        isa = SVP64Asm(['sv.add/dm=ne 1.v, 5.v, 9.v'
+        isa = SVP64Asm(['sv.add/m=ne 1.v, 5.v, 9.v'
                        ])
         lst = list(isa)
         print ("listing", lst)

diff --git a/src/soc/sv/trans/svp64.py b/src/soc/sv/trans/svp64.py
index 2e9bea074fc0a28312233c2b61925288a1052a29..da4311b7f61ef3776a03eb07e8fcd6d890df1cae 100644 (file)
--- a/src/soc/sv/trans/svp64.py
+++ b/src/soc/sv/trans/svp64.py
@@ -493,6 +493,8 @@ class SVP64Asm:
             if ptype == '1P':
                 assert not has_smask, \
                     "source-mask can only be specified on Twin-predicate ops"
+                assert not has_pmask, \
+                    "dest-mask can only be specified on Twin-predicate ops"
 
             # construct the mode field, doing sanity-checking along the way