soc.git
4 years agoadd comment about SPRs CSV
Luke Kenneth Casson Leighton [Wed, 18 Mar 2020 12:12:21 +0000 (12:12 +0000)]
add comment about SPRs CSV

4 years agoadd comments
Luke Kenneth Casson Leighton [Wed, 18 Mar 2020 12:03:42 +0000 (12:03 +0000)]
add comments

4 years agoimport absolute paths
Luke Kenneth Casson Leighton [Wed, 18 Mar 2020 11:30:58 +0000 (11:30 +0000)]
import absolute paths

4 years agoclarify is_match manually
Luke Kenneth Casson Leighton [Mon, 16 Mar 2020 17:19:43 +0000 (17:19 +0000)]
clarify is_match manually

4 years agoadd exploratory unit test for partial address matching
Luke Kenneth Casson Leighton [Mon, 16 Mar 2020 13:18:48 +0000 (13:18 +0000)]
add exploratory unit test for partial address matching

4 years agocomment out addr_we_i, seems not to be used
Luke Kenneth Casson Leighton [Mon, 16 Mar 2020 12:39:28 +0000 (12:39 +0000)]
comment out addr_we_i, seems not to be used

4 years agoconnect up expander output, set up is_match to check bitmap and wrapped bitmap
Luke Kenneth Casson Leighton [Mon, 16 Mar 2020 12:39:03 +0000 (12:39 +0000)]
connect up expander output, set up is_match to check bitmap and wrapped bitmap
(crossing cache line boundary)

4 years agoconnect LenExpanders into PartialAddrBitmap
Luke Kenneth Casson Leighton [Mon, 16 Mar 2020 12:12:43 +0000 (12:12 +0000)]
connect LenExpanders into PartialAddrBitmap

4 years agocrossreference to bugreport
Luke Kenneth Casson Leighton [Sun, 15 Mar 2020 22:16:20 +0000 (22:16 +0000)]
crossreference to bugreport

4 years agoadd description of how PartialAddrBitmap works
Luke Kenneth Casson Leighton [Sun, 15 Mar 2020 22:15:42 +0000 (22:15 +0000)]
add description of how PartialAddrBitmap works

4 years ago add beginnings of link to lenexpanders
Luke Kenneth Casson Leighton [Sun, 15 Mar 2020 11:20:02 +0000 (11:20 +0000)]
 add beginnings of link to lenexpanders

4 years agoadd a LenExpand class which takes a (length, addr) pair,
Luke Kenneth Casson Leighton [Sat, 14 Mar 2020 17:50:58 +0000 (17:50 +0000)]
add a LenExpand class which takes a (length, addr) pair,
turns it into a bitmap of bytes that would be affected by that LD/ST

4 years agoadd beginnings of PartialAddrBitmap elaborate
Luke Kenneth Casson Leighton [Sat, 14 Mar 2020 11:56:07 +0000 (11:56 +0000)]
add beginnings of PartialAddrBitmap elaborate

4 years agoallow over-ride of address match function in PartialAddrMatch
Luke Kenneth Casson Leighton [Fri, 13 Mar 2020 22:36:19 +0000 (22:36 +0000)]
allow over-ride of address match function in PartialAddrMatch

4 years agofix more imports
Luke Kenneth Casson Leighton [Wed, 11 Mar 2020 18:19:08 +0000 (18:19 +0000)]
fix more imports

4 years agofix more imports
Luke Kenneth Casson Leighton [Wed, 11 Mar 2020 18:18:14 +0000 (18:18 +0000)]
fix more imports

4 years agoenable rvfi, fix imports
Luke Kenneth Casson Leighton [Wed, 11 Mar 2020 18:16:35 +0000 (18:16 +0000)]
enable rvfi, fix imports

4 years agodestarify debug
Luke Kenneth Casson Leighton [Wed, 11 Mar 2020 18:15:17 +0000 (18:15 +0000)]
destarify debug

4 years agodewildcardify units
Luke Kenneth Casson Leighton [Wed, 11 Mar 2020 17:17:46 +0000 (17:17 +0000)]
dewildcardify units

4 years agodewildcardify unitsg
Luke Kenneth Casson Leighton [Wed, 11 Mar 2020 17:10:35 +0000 (17:10 +0000)]
dewildcardify unitsg

4 years agosort out imports to get minerva generate working
Luke Kenneth Casson Leighton [Wed, 11 Mar 2020 17:05:20 +0000 (17:05 +0000)]
sort out imports to get minerva generate working

4 years agodewildcard core.py
Luke Kenneth Casson Leighton [Wed, 11 Mar 2020 17:02:24 +0000 (17:02 +0000)]
dewildcard core.py

4 years agodewildcard cache.py
Luke Kenneth Casson Leighton [Wed, 11 Mar 2020 16:54:29 +0000 (16:54 +0000)]
dewildcard cache.py

4 years agodewildcard stage.py
Luke Kenneth Casson Leighton [Wed, 11 Mar 2020 16:51:57 +0000 (16:51 +0000)]
dewildcard stage.py

4 years agodewildcard wishbone.py
Luke Kenneth Casson Leighton [Wed, 11 Mar 2020 16:49:49 +0000 (16:49 +0000)]
dewildcard wishbone.py

4 years agoreplace isa import
Luke Kenneth Casson Leighton [Wed, 11 Mar 2020 16:44:27 +0000 (16:44 +0000)]
replace isa import

4 years agode-starify csr.py
Luke Kenneth Casson Leighton [Wed, 11 Mar 2020 16:28:25 +0000 (16:28 +0000)]
de-starify csr.py

4 years agoimport minerva from soc.minerva
Luke Kenneth Casson Leighton [Wed, 11 Mar 2020 16:13:16 +0000 (16:13 +0000)]
import minerva from soc.minerva

4 years agoadd minerva source from https://github.com/lambdaconcept/minerva
Luke Kenneth Casson Leighton [Wed, 11 Mar 2020 16:10:51 +0000 (16:10 +0000)]
add minerva source from https://github.com/lambdaconcept/minerva

4 years agoAdd assertions that instruction fields are correct
Michael Nolan [Wed, 11 Mar 2020 14:17:26 +0000 (10:17 -0400)]
Add assertions that instruction fields are correct

4 years agoAdd test for remaining bits
Michael Nolan [Wed, 11 Mar 2020 13:21:35 +0000 (09:21 -0400)]
Add test for remaining bits

4 years agoAdd tests for DecodeOut and DecodeRC
Michael Nolan [Wed, 11 Mar 2020 13:12:52 +0000 (09:12 -0400)]
Add tests for DecodeOut and DecodeRC

4 years agostore ra in intermediate, to avoid creation of decoding twice
Luke Kenneth Casson Leighton [Wed, 11 Mar 2020 08:37:24 +0000 (08:37 +0000)]
store ra in intermediate, to avoid creation of decoding twice

4 years agoadd "done" signal to CompALU and LDSTCompALU to be able to select between the
Luke Kenneth Casson Leighton [Tue, 10 Mar 2020 20:38:05 +0000 (20:38 +0000)]
add "done" signal to CompALU and LDSTCompALU to be able to select between the
two types consistently

4 years agoinitial test LD comp unit in scoreboard
Luke Kenneth Casson Leighton [Tue, 10 Mar 2020 19:49:55 +0000 (19:49 +0000)]
initial test LD comp unit in scoreboard

4 years agohmmm set store latch based on go_rd_i
Luke Kenneth Casson Leighton [Tue, 10 Mar 2020 18:10:15 +0000 (18:10 +0000)]
hmmm set store latch based on go_rd_i

4 years agoadd ADD/ADDI test to LDSTCompUnit
Luke Kenneth Casson Leighton [Tue, 10 Mar 2020 18:00:54 +0000 (18:00 +0000)]
add ADD/ADDI test to LDSTCompUnit

4 years agoamazingly got LD working on LDSTCompUnit
Luke Kenneth Casson Leighton [Tue, 10 Mar 2020 16:27:15 +0000 (16:27 +0000)]
amazingly got LD working on LDSTCompUnit

4 years agocomments explaining what alu_hier.py does
Luke Kenneth Casson Leighton [Tue, 10 Mar 2020 16:27:00 +0000 (16:27 +0000)]
comments explaining what alu_hier.py does

4 years agoLD appears to be working as well although there is an oddness in the gtkwave
Luke Kenneth Casson Leighton [Tue, 10 Mar 2020 16:08:03 +0000 (16:08 +0000)]
LD appears to be working as well although there is an oddness in the gtkwave
output, data_o is not showing as changing despite the simulation
getting the correct output

4 years agowhoops as simple as having inverted the LD/ST bit in oper_r
Luke Kenneth Casson Leighton [Tue, 10 Mar 2020 15:51:15 +0000 (15:51 +0000)]
whoops as simple as having inverted the LD/ST bit in oper_r

4 years agoAdd cases for DecodeB and DecodeC
Michael Nolan [Tue, 10 Mar 2020 15:22:44 +0000 (11:22 -0400)]
Add cases for DecodeB and DecodeC

4 years agoRefactor DecodeA test
Michael Nolan [Tue, 10 Mar 2020 15:07:05 +0000 (11:07 -0400)]
Refactor DecodeA test

4 years agoAdd proof for power_decoder2.DecodeA
Michael Nolan [Mon, 9 Mar 2020 15:14:38 +0000 (11:14 -0400)]
Add proof for power_decoder2.DecodeA

4 years agohmm not quite right, errr ST is working when setting op to LD... err...
Luke Kenneth Casson Leighton [Tue, 10 Mar 2020 14:31:00 +0000 (14:31 +0000)]
hmm not quite right, errr ST is working when setting op to LD... err...

4 years agoget LDSTCompALU debugged a bit: ST functionality working
Luke Kenneth Casson Leighton [Tue, 10 Mar 2020 12:57:12 +0000 (12:57 +0000)]
get LDSTCompALU debugged a bit: ST functionality working

4 years agoadd comment on oper_i field
Luke Kenneth Casson Leighton [Mon, 9 Mar 2020 20:25:36 +0000 (20:25 +0000)]
add comment on oper_i field

4 years agodisable transparent=False for now
Luke Kenneth Casson Leighton [Mon, 9 Mar 2020 20:22:27 +0000 (20:22 +0000)]
disable transparent=False for now

4 years agoconnect up LD to memory: set transparent mode to False.
Luke Kenneth Casson Leighton [Mon, 9 Mar 2020 16:28:45 +0000 (16:28 +0000)]
connect up LD to memory: set transparent mode to False.
need to check if the memory is valid one clock later

4 years agomore comments for LDSTCompUnit
Luke Kenneth Casson Leighton [Mon, 9 Mar 2020 16:17:12 +0000 (16:17 +0000)]
more comments for LDSTCompUnit

4 years agoupdate LDSTCompUnit comments
Luke Kenneth Casson Leighton [Mon, 9 Mar 2020 16:12:30 +0000 (16:12 +0000)]
update LDSTCompUnit comments

4 years agotry adding test memory store to LDSTCompUnit
Luke Kenneth Casson Leighton [Mon, 9 Mar 2020 15:41:11 +0000 (15:41 +0000)]
try adding test memory store to LDSTCompUnit

4 years agoFix logical loop in DecodeA
Michael Nolan [Mon, 9 Mar 2020 15:00:55 +0000 (11:00 -0400)]
Fix logical loop in DecodeA

4 years agoBegin adding proof for decoder2
Michael Nolan [Mon, 9 Mar 2020 14:55:45 +0000 (10:55 -0400)]
Begin adding proof for decoder2

4 years agoMigrate imports to use absolute imports
Michael Nolan [Mon, 9 Mar 2020 14:54:02 +0000 (10:54 -0400)]
Migrate imports to use absolute imports

4 years agoFix test
Michael Nolan [Mon, 9 Mar 2020 13:54:23 +0000 (09:54 -0400)]
Fix test

4 years agosort imports on scoreboard
Luke Kenneth Casson Leighton [Mon, 9 Mar 2020 13:52:28 +0000 (13:52 +0000)]
sort imports on scoreboard

4 years agoadd __init__.py files to decoder
Luke Kenneth Casson Leighton [Mon, 9 Mar 2020 13:47:41 +0000 (13:47 +0000)]
add __init__.py files to decoder

4 years agoadd __init__.py to soc
Luke Kenneth Casson Leighton [Mon, 9 Mar 2020 13:43:07 +0000 (13:43 +0000)]
add __init__.py to soc

4 years agomove all source directories to soc so that "import soc.scoreboard" etc is used
Luke Kenneth Casson Leighton [Mon, 9 Mar 2020 13:42:31 +0000 (13:42 +0000)]
move all source directories to soc so that "import soc.scoreboard" etc is used

4 years agoconvert SPRs and others to Data.data/ok
Luke Kenneth Casson Leighton [Sun, 8 Mar 2020 20:18:34 +0000 (20:18 +0000)]
convert SPRs and others to Data.data/ok

4 years agoconvert to output reg/imm data plus "ok" flag
Luke Kenneth Casson Leighton [Sun, 8 Mar 2020 19:11:03 +0000 (19:11 +0000)]
convert to output reg/imm data plus "ok" flag

4 years agolikewise comment out CR from decode, it is from the CR SPR regfile
Luke Kenneth Casson Leighton [Sun, 8 Mar 2020 18:29:23 +0000 (18:29 +0000)]
likewise comment out CR from decode, it is from the CR SPR regfile

4 years agotake XER out of decode, it is from the CR regfile
Luke Kenneth Casson Leighton [Sun, 8 Mar 2020 18:27:15 +0000 (18:27 +0000)]
take XER out of decode, it is from the CR regfile

4 years agoadd test conversion to ilang to PowerDecoder2, fix resultant errors
Luke Kenneth Casson Leighton [Sun, 8 Mar 2020 18:13:40 +0000 (18:13 +0000)]
add test conversion to ilang to PowerDecoder2, fix resultant errors

4 years agoadd class comments, add rtlil creator for PowerDecode2
Luke Kenneth Casson Leighton [Sun, 8 Mar 2020 17:51:57 +0000 (17:51 +0000)]
add class comments, add rtlil creator for PowerDecode2

4 years agoadd combined instruction and register decoder
Luke Kenneth Casson Leighton [Sun, 8 Mar 2020 17:33:38 +0000 (17:33 +0000)]
add combined instruction and register decoder

4 years agowhitespace
Luke Kenneth Casson Leighton [Sun, 8 Mar 2020 15:25:59 +0000 (15:25 +0000)]
whitespace

4 years agodecode b, c, out, rc and oe
Luke Kenneth Casson Leighton [Sun, 8 Mar 2020 15:25:38 +0000 (15:25 +0000)]
decode b, c, out, rc and oe

4 years agoadd spr decode to A
Luke Kenneth Casson Leighton [Sun, 8 Mar 2020 13:17:31 +0000 (13:17 +0000)]
add spr decode to A

4 years agoadd SPR enum
Luke Kenneth Casson Leighton [Sun, 8 Mar 2020 12:53:38 +0000 (12:53 +0000)]
add SPR enum

4 years agostart adding DecodeA
Luke Kenneth Casson Leighton [Sun, 8 Mar 2020 12:33:34 +0000 (12:33 +0000)]
start adding DecodeA

4 years agoadd start on power decoder2
Luke Kenneth Casson Leighton [Sun, 8 Mar 2020 11:42:46 +0000 (11:42 +0000)]
add start on power decoder2

4 years agoadd extra field-register sh
Luke Kenneth Casson Leighton [Sat, 7 Mar 2020 22:27:20 +0000 (22:27 +0000)]
add extra field-register sh

4 years agoadd shortcuts to opcode fields from insn_helpes.vhdl
Luke Kenneth Casson Leighton [Sat, 7 Mar 2020 21:34:39 +0000 (21:34 +0000)]
add shortcuts to opcode fields from insn_helpes.vhdl

4 years agolink in power field decoder
Luke Kenneth Casson Leighton [Sat, 7 Mar 2020 21:07:54 +0000 (21:07 +0000)]
link in power field decoder

4 years agoadd example usage of power_fields to get at named parts of opcode
Luke Kenneth Casson Leighton [Sat, 7 Mar 2020 15:58:47 +0000 (15:58 +0000)]
add example usage of power_fields to get at named parts of opcode

4 years agoadd class which creates useable (named) representation of fields
Luke Kenneth Casson Leighton [Sat, 7 Mar 2020 14:50:12 +0000 (14:50 +0000)]
add class which creates useable (named) representation of fields

4 years agouniquify names
Luke Kenneth Casson Leighton [Sat, 7 Mar 2020 13:21:38 +0000 (13:21 +0000)]
uniquify names

4 years agoadd decoder on power fields
Luke Kenneth Casson Leighton [Fri, 6 Mar 2020 19:28:11 +0000 (19:28 +0000)]
add decoder on power fields

4 years agoadd field decoder
Luke Kenneth Casson Leighton [Fri, 6 Mar 2020 18:37:43 +0000 (18:37 +0000)]
add field decoder

4 years agoprocess fields to get positions associated with format
Luke Kenneth Casson Leighton [Thu, 5 Mar 2020 23:08:22 +0000 (23:08 +0000)]
process fields to get positions associated with format

4 years agodecode power fields from Forms, section 1.6 of 2.07B ISA
Luke Kenneth Casson Leighton [Thu, 5 Mar 2020 21:56:02 +0000 (21:56 +0000)]
decode power fields from Forms, section 1.6 of 2.07B ISA

4 years agocorrections on Form PowerDecoder
Luke Kenneth Casson Leighton [Thu, 5 Mar 2020 18:42:14 +0000 (18:42 +0000)]
corrections on Form PowerDecoder

4 years agowhoops wrong numbering
Luke Kenneth Casson Leighton [Thu, 5 Mar 2020 18:36:42 +0000 (18:36 +0000)]
whoops wrong numbering

4 years agoadd "form" to power decode
Luke Kenneth Casson Leighton [Thu, 5 Mar 2020 18:35:55 +0000 (18:35 +0000)]
add "form" to power decode

4 years agoadd more comments
Luke Kenneth Casson Leighton [Thu, 5 Mar 2020 12:30:05 +0000 (12:30 +0000)]
add more comments

4 years agoadd comment docstring explaining power decoder
Luke Kenneth Casson Leighton [Thu, 5 Mar 2020 12:14:35 +0000 (12:14 +0000)]
add comment docstring explaining power decoder

4 years agowhitespace
Luke Kenneth Casson Leighton [Thu, 5 Mar 2020 03:55:48 +0000 (03:55 +0000)]
whitespace

4 years agoadd minor_19 patterns and extra/major
Luke Kenneth Casson Leighton [Thu, 5 Mar 2020 03:51:53 +0000 (03:51 +0000)]
add minor_19 patterns and extra/major

4 years ago3am coding. sigh. converted PowerDecoder to take list of namedtuples
Luke Kenneth Casson Leighton [Thu, 5 Mar 2020 03:35:17 +0000 (03:35 +0000)]
3am coding. sigh.  converted PowerDecoder to take list of namedtuples
can now pass in extra.csv and major.csv in setup

4 years agoadd idea of Decoder namedtuple
Luke Kenneth Casson Leighton [Wed, 4 Mar 2020 19:12:36 +0000 (19:12 +0000)]
add idea of Decoder namedtuple

4 years agowhoops realised that it is *PowerDecoder* args that need to become a list
Luke Kenneth Casson Leighton [Wed, 4 Mar 2020 17:32:00 +0000 (17:32 +0000)]
whoops realised that it is *PowerDecoder* args that need to become a list

4 years agomove default case out of switch, to make room for multiple switches
Luke Kenneth Casson Leighton [Wed, 4 Mar 2020 16:49:01 +0000 (16:49 +0000)]
move default case out of switch, to make room for multiple switches
and a *list* of subdecoders

4 years agoAdd suffix handling back in
Michael Nolan [Wed, 4 Mar 2020 16:09:20 +0000 (11:09 -0500)]
Add suffix handling back in

4 years agoGenerate ilang for whole decoder
Michael Nolan [Wed, 4 Mar 2020 16:09:06 +0000 (11:09 -0500)]
Generate ilang for whole decoder

4 years agoAdd tests for minor_58 and minor_62
Michael Nolan [Wed, 4 Mar 2020 15:42:47 +0000 (10:42 -0500)]
Add tests for minor_58 and minor_62

4 years agoHierarchial decoder semi-working
Michael Nolan [Wed, 4 Mar 2020 15:31:15 +0000 (10:31 -0500)]
Hierarchial decoder semi-working

4 years agoAdd bit selectors for most of the tests
Michael Nolan [Wed, 4 Mar 2020 14:40:23 +0000 (09:40 -0500)]
Add bit selectors for most of the tests

4 years agoChange decoder to take the bits to select of the opcode as parameter
Michael Nolan [Wed, 4 Mar 2020 14:36:33 +0000 (09:36 -0500)]
Change decoder to take the bits to select of the opcode as parameter