soc.git
2020-07-24 Jacob Lifshayadd power-instruction-analyzer as a dependency
2020-07-24 Jacob Lifshayformat
2020-07-23 Luke Kenneth... syntax error
2020-07-23 Luke Kenneth... support 32-bit mem width setting
2020-07-23 Luke Kenneth... try SDRAM SDR
2020-07-23 Luke Kenneth... allow imem to be 64/32 bit wide
2020-07-23 Luke Kenneth... begin core in running state
2020-07-23 Luke Kenneth... try different MEMTEST_xxx sizes with 64 bit bus width
2020-07-23 Cole PoirierUpdate libreriscv HDL_workflow/coriolis2
2020-07-23 Jacob Lifshayadd all div* and mod* instructions to test_pipe_caller
2020-07-22 Jacob Lifshayworking on fsm
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master'
2020-07-22 Jacob Lifshayformat code
2020-07-22 Luke Kenneth... re-add CRG (clock reset generator)
2020-07-22 Luke Kenneth... missing ports from issuer, when doing verilog
2020-07-22 Luke Kenneth... add clock domain using snippet taken from random file
2020-07-22 Luke Kenneth... cleanup in litex core.py
2020-07-22 Luke Kenneth... update comments
2020-07-22 Luke Kenneth... add dummy irq set/get
2020-07-22 Luke Kenneth... add boot-helper.S etc from microwatt litex core
2020-07-22 Luke Kenneth... set additional MSR bits according to v3.0B spec when...
2020-07-22 Luke Kenneth... use (new) MSRb and PIb which has auto-bigendian numbers
2020-07-22 Luke Kenneth... sigh, auto-create some little/big-endian classes for...
2020-07-22 Luke Kenneth... missed import of Builder, set cpu_type to "None" tempor...
2020-07-22 Luke Kenneth... begin converting litex sim to libre-soc
2020-07-22 Luke Kenneth... whoops forgot field accessor
2020-07-22 Luke Kenneth... do not use wildcard import
2020-07-22 Luke Kenneth... start from vexriscv sim.py from
2020-07-22 Luke Kenneth... correct syntax error
2020-07-22 Luke Kenneth... first version of litex core (to be submitted upstream...
2020-07-22 Luke Kenneth... whoops typo, 63-start not 3-start (doh)
2020-07-22 Luke Kenneth... field number ordering wrong way round?
2020-07-22 Luke Kenneth... syntax error
2020-07-22 Luke Kenneth... review trap main_stage.py modifications: we are not...
2020-07-22 Luke Kenneth... comments, add page spec numbers for branch ops into...
2020-07-22 Luke Kenneth... add comment headings with spec page numbers
2020-07-22 Luke Kenneth... comment on op.insn ordering
2020-07-22 Luke Kenneth... code-shuffle, add comments
2020-07-22 Luke Kenneth... add TT.size and use it in PowerDecoder and trap input...
2020-07-22 Luke Kenneth... inline comments in trap proof
2020-07-22 Luke Kenneth... note that traptype MUST increase in bitwidth correspond...
2020-07-22 Luke Kenneth... fix branch main_stage proof, add ctr 32-bit, fix BCREG
2020-07-22 Luke Kenneth... rework branch proof to use br_input_record
2020-07-22 Luke Kenneth... update README for pipe_data.py
2020-07-22 Luke Kenneth... reduce number of FastRegs read ports
2020-07-22 Luke Kenneth... comments on what goes into CommonPipeSpec
2020-07-22 Samuel A. Falvo IIComplete FV properties for OP_TRAP instructions.
2020-07-22 Samuel A. Falvo IIPEP8 compliance
2020-07-22 Jacob Lifshayworking on FSMDivCoreStage
2020-07-22 Jacob Lifshayfix test_div_state_fsm
2020-07-21 Samuel A. Falvo IICompleted SC FV properties
2020-07-21 Samuel A. Falvo IIRefine properties to comply with spec
2020-07-21 Samuel A. Falvo IIFix where msr_i gets its value from
2020-07-21 Samuel A. Falvo IIMerge in recent updates to TRAP FV properties.
2020-07-21 Luke Kenneth... convert branch pipeline to use msr/cia as immediates
2020-07-21 Luke Kenneth... put set_msr and set_cia back in for now
2020-07-21 Luke Kenneth... interesting bug in test_compunit.py when there are...
2020-07-21 Luke Kenneth... testing if MultiCompUnit can handle no input regs ...
2020-07-21 Luke Kenneth... disable cxxsim for now
2020-07-21 Luke Kenneth... move cia and msr to trap input record
2020-07-21 Luke Kenneth... set ISACaller.msr rather than namespace[MSR]
2020-07-21 Luke Kenneth... when running an exception (trap) after "reset" must...
2020-07-21 Luke Kenneth... spurious imports of FHDLTestCase, should be from nmutil
2020-07-21 Luke Kenneth... whitespace
2020-07-21 Luke Kenneth... add PC (CIA) to PowerDecode2 "state" for passing into...
2020-07-21 Luke Kenneth... add msr exception bits setting function in hardware
2020-07-21 Luke Kenneth... make cxxsim optional and print warning
2020-07-21 Luke Kenneth... corrections to trap proof see
2020-07-21 Luke Kenneth... use alias for msr_i in trap proof
2020-07-21 Luke Kenneth... correct trap spec page interrupt ref
2020-07-20 Samuel A. Falvo IIRework SC properties to conform to style
2020-07-20 Samuel A. Falvo IIFormal properties for RFID.
2020-07-20 Cesar StraussDocument the move of sdir from data_i to op.
2020-07-20 Cesar StraussRemove extra yield from test case.
2020-07-19 Luke Kenneth... do not start core in terminated mode
2020-07-19 Luke Kenneth... explicitly set up a pc_i_ok signal in test_microwatt.py
2020-07-19 Luke Kenneth... expose core_stop_i to outside as well
2020-07-19 Luke Kenneth... set go_insn_i to non-resetless
2020-07-19 Luke Kenneth... add issuer verilog generator
2020-07-19 Luke Kenneth... update to expose signals at top-level of issuer
2020-07-19 Luke Kenneth... convert compalu multi test to Simulator() (was run_simu...
2020-07-19 Luke Kenneth... convert compalu multi test to Simulator() (was run_simu...
2020-07-19 Luke Kenneth... use same write_vcd for cxxsim as pysim
2020-07-19 Luke Kenneth... fix bug in alu_fsm.py found by cxxsim: missing one...
2020-07-19 Luke Kenneth... add some CompUnit demo tests of the alu_fsm example
2020-07-19 Luke Kenneth... move sdir to CompFSMOpSubset in alu_fsm example
2020-07-19 Luke Kenneth... add CompFSMOpSubset, also change dir to sdir
2020-07-19 Luke Kenneth... remove unneeded import
2020-07-19 Luke Kenneth... if nmigen.sim.pysim import fails use nmigen.back.pysim
2020-07-19 Luke Kenneth... use iocontrol PrevControl / NextControl instead of...
2020-07-19 Luke Kenneth... add DivTestCase to test_issuer.py (commented out for...
2020-07-19 Cesar StraussImplement control path and unit test.
2020-07-18 Luke Kenneth... worked out that DivPipeSpec can be given a default...
2020-07-18 Luke Kenneth... missing conversion of DIV to Div
2020-07-18 Luke Kenneth... add option to generate verilog
2020-07-18 Luke Kenneth... whoops use slice not range
2020-07-18 Luke Kenneth... syntax error
2020-07-18 Cesar StraussImplement the Shifter data path
2020-07-18 Cesar StraussDocument move of the next port data
2020-07-18 Luke Kenneth... add SR latch cxxrtl backend demo
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