rename pll out signal to out_v in "fake" pll cell

diff --git a/experiments9/pll.py b/experiments9/pll.py
index 0bc3cff750c082140ffa35dce502aa5be45438cc..86944b3287357d2e4b3b62e47065b4588ecb11ab 100644 (file)
--- a/experiments9/pll.py
+++ b/experiments9/pll.py
@@ -220,14 +220,15 @@ def _load():
             'a0': Net.create(cell, 'a0'),
             'a1': Net.create(cell, 'a1'),
             'vco_test_ana': Net.create(cell, 'vco_test_ana'),
-            'out': Net.create(cell, 'out'),
+            'out_v': Net.create(cell, 'out_v'),
         }
 
         # create series of stepped pins
         x = 0.135*20
         wid = 0.135 / 2
         step = wid*10
-        for cname in ['ref', 'div_out_test', 'a0', 'a1', 'vco_test_ana', 'out']:
+        for cname in ['ref', 'div_out_test', 'a0', 'a1', 'vco_test_ana',
+                      'out_v']:
             net = nets[cname]
             pin = Vertical.create(
                 net, tech.getLayer('metal1'),