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Rebame root clock signal from "core.por_clk" into "core.pll_clk".
authorJean-Paul Chaput <Jean-Paul.Chaput@lip6.fr>
Thu, 10 Jun 2021 09:17:20 +0000 (11:17 +0200)
committerJean-Paul Chaput <Jean-Paul.Chaput@lip6.fr>
Thu, 10 Jun 2021 09:17:20 +0000 (11:17 +0200)
experiments9/tsmc_c018/doDesign.py patch | blob | history

diff --git a/experiments9/tsmc_c018/doDesign.py b/experiments9/tsmc_c018/doDesign.py
index a48b14ffaf3043c875da45a50020df0e122902ce..d4230f2153b1937c393b1254d98fa47cedbd3012 100644 (file)
--- a/experiments9/tsmc_c018/doDesign.py
+++ b/experiments9/tsmc_c018/doDesign.py
@@ -243,10 +243,7 @@ def scriptMain (**kw):
         ls180Conf.chipConf.ioPadGauge = 'LibreSOCIO'
         ls180Conf.coreSize = (coreSizeX, coreSizeY)
         ls180Conf.chipSize = (coreSizeX + chipBorder + u(5.0), coreSizeY + chipBorder - u(0.04) )
-       #ls180Conf.useHTree( 'core.subckt_12941_test_issuer.ti_coresync_clk' )
-        # XXX this is probably just por_clk not core.por_clk
-        # or, more likely, core.pllclk_clk
-        ls180Conf.useHTree( 'core.por_clk' )
+        ls180Conf.useHTree( 'core.pll_clk' )
         ls180Conf.useHTree( 'jtag_tck_from_pad' )
 
         tiPath = 'test_issuer.ti.'