22e0ab42f5c4482c24d457cdd37df197a7cbbbb9
[sv2nmigen.git] / examples / assignment2.sv
1 module assignment(
2 output o,
3 input i
4 );
5 wire x,y;
6 wire [15:0] z;
7 assign x = i;
8 assign o = x;
9 endmodule