4 * Copyright (c) 1998-2017 Stephen Williams (steve@icarus.com)
5 * Copyright CERN 2012-2013 / Stephen Williams (steve@icarus.com)
7 * This source code is free software; you can redistribute it
8 * and/or modify it in source code form under the terms of the GNU
9 * General Public License as published by the Free Software
10 * Foundation; either version 2 of the License, or (at your option)
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
25 # include "parse_misc.h"
26 # include "compiler.h"
28 # include "Statement.h"
36 extern void lex_end_table();
38 static list<pform_range_t>* param_active_range = 0;
39 static bool param_active_signed = false;
40 static ivl_variable_type_t param_active_type = IVL_VT_LOGIC;
42 /* Port declaration lists use this structure for context. */
44 NetNet::Type port_net_type;
45 NetNet::PortType port_type;
46 data_type_t* data_type;
47 } port_declaration_context = {NetNet::NONE, NetNet::NOT_A_PORT, 0};
49 /* Modport port declaration lists use this structure for context. */
50 enum modport_port_type_t { MP_NONE, MP_SIMPLE, MP_TF, MP_CLOCKING };
52 modport_port_type_t type;
54 NetNet::PortType direction;
57 } last_modport_port = { MP_NONE, {NetNet::NOT_A_PORT}};
59 /* The task and function rules need to briefly hold the pointer to the
60 task/function that is currently in progress. */
61 static PTask* current_task = 0;
62 static PFunction* current_function = 0;
63 static stack<PBlock*> current_block_stack;
65 /* The variable declaration rules need to know if a lifetime has been
67 static LexicalScope::lifetime_t var_lifetime;
69 static pform_name_t* pform_create_this(void)
71 name_component_t name (perm_string::literal("@"));
72 pform_name_t*res = new pform_name_t;
77 static pform_name_t* pform_create_super(void)
79 name_component_t name (perm_string::literal("#"));
80 pform_name_t*res = new pform_name_t;
85 /* This is used to keep track of the extra arguments after the notifier
86 * in the $setuphold and $recrem timing checks. This allows us to print
87 * a warning message that the delayed signals will not be created. We
88 * need to do this since not driving these signals creates real
89 * simulation issues. */
90 static unsigned args_after_notifier;
92 /* The rules sometimes push attributes into a global context where
93 sub-rules may grab them. This makes parser rules a little easier to
94 write in some cases. */
95 static list<named_pexpr_t>*attributes_in_context = 0;
97 /* Later version of bison (including 1.35) will not compile in stack
98 extension if the output is compiled with C++ and either the YYSTYPE
99 or YYLTYPE are provided by the source code. However, I can get the
100 old behavior back by defining these symbols. */
101 # define YYSTYPE_IS_TRIVIAL 1
102 # define YYLTYPE_IS_TRIVIAL 1
104 /* Recent version of bison expect that the user supply a
105 YYLLOC_DEFAULT macro that makes up a yylloc value from existing
106 values. I need to supply an explicit version to account for the
107 text field, that otherwise won't be copied.
109 The YYLLOC_DEFAULT blends the file range for the tokens of Rhs
110 rule, which has N tokens.
112 # define YYLLOC_DEFAULT(Current, Rhs, N) do { \
114 (Current).first_line = YYRHSLOC (Rhs, 1).first_line; \
115 (Current).first_column = YYRHSLOC (Rhs, 1).first_column; \
116 (Current).last_line = YYRHSLOC (Rhs, N).last_line; \
117 (Current).last_column = YYRHSLOC (Rhs, N).last_column; \
118 (Current).text = YYRHSLOC (Rhs, 1).text; \
120 (Current).first_line = YYRHSLOC (Rhs, 0).last_line; \
121 (Current).first_column = YYRHSLOC (Rhs, 0).last_column; \
122 (Current).last_line = YYRHSLOC (Rhs, 0).last_line; \
123 (Current).last_column = YYRHSLOC (Rhs, 0).last_column; \
124 (Current).text = YYRHSLOC (Rhs, 0).text; \
129 * These are some common strength pairs that are used as defaults when
130 * the user is not otherwise specific.
132 static const struct str_pair_t pull_strength = { IVL_DR_PULL, IVL_DR_PULL };
133 static const struct str_pair_t str_strength = { IVL_DR_STRONG, IVL_DR_STRONG };
135 static list<pform_port_t>* make_port_list(char*id, list<pform_range_t>*udims, PExpr*expr)
137 list<pform_port_t>*tmp = new list<pform_port_t>;
138 tmp->push_back(pform_port_t(lex_strings.make(id), udims, expr));
142 static list<pform_port_t>* make_port_list(list<pform_port_t>*tmp,
143 char*id, list<pform_range_t>*udims, PExpr*expr)
145 tmp->push_back(pform_port_t(lex_strings.make(id), udims, expr));
150 list<pform_range_t>* make_range_from_width(uint64_t wid)
153 range.first = new PENumber(new verinum(wid-1, integer_width));
154 range.second = new PENumber(new verinum((uint64_t)0, integer_width));
156 list<pform_range_t>*rlist = new list<pform_range_t>;
157 rlist->push_back(range);
161 static list<perm_string>* list_from_identifier(char*id)
163 list<perm_string>*tmp = new list<perm_string>;
164 tmp->push_back(lex_strings.make(id));
169 static list<perm_string>* list_from_identifier(list<perm_string>*tmp, char*id)
171 tmp->push_back(lex_strings.make(id));
176 list<pform_range_t>* copy_range(list<pform_range_t>* orig)
178 list<pform_range_t>*copy = 0;
181 copy = new list<pform_range_t> (*orig);
186 template <class T> void append(vector<T>&out, const vector<T>&in)
188 for (size_t idx = 0 ; idx < in.size() ; idx += 1)
189 out.push_back(in[idx]);
193 * Look at the list and pull null pointers off the end.
195 static void strip_tail_items(list<PExpr*>*lst)
197 while (! lst->empty()) {
198 if (lst->back() != 0)
205 * This is a shorthand for making a PECallFunction that takes a single
206 * arg. This is used by some of the code that detects built-ins.
208 static PECallFunction*make_call_function(perm_string tn, PExpr*arg)
210 vector<PExpr*> parms(1);
212 PECallFunction*tmp = new PECallFunction(tn, parms);
216 static PECallFunction*make_call_function(perm_string tn, PExpr*arg1, PExpr*arg2)
218 vector<PExpr*> parms(2);
221 PECallFunction*tmp = new PECallFunction(tn, parms);
225 static list<named_pexpr_t>* make_named_numbers(perm_string name, long first, long last, PExpr*val =0)
227 list<named_pexpr_t>*lst = new list<named_pexpr_t>;
229 // We are counting up.
231 for (long idx = first ; idx <= last ; idx += 1) {
233 buf << name.str() << idx << ends;
234 tmp.name = lex_strings.make(buf.str());
239 // We are counting down.
241 for (long idx = first ; idx >= last ; idx -= 1) {
243 buf << name.str() << idx << ends;
244 tmp.name = lex_strings.make(buf.str());
253 static list<named_pexpr_t>* make_named_number(perm_string name, PExpr*val =0)
255 list<named_pexpr_t>*lst = new list<named_pexpr_t>;
263 static long check_enum_seq_value(const YYLTYPE&loc, verinum *arg, bool zero_ok)
266 // We can never have an undefined value in an enumeration name
267 // declaration sequence.
268 if (! arg->is_defined()) {
269 yyerror(loc, "error: undefined value used in enum name sequence.");
270 // We can never have a negative value in an enumeration name
271 // declaration sequence.
272 } else if (arg->is_negative()) {
273 yyerror(loc, "error: negative value used in enum name sequence.");
275 value = arg->as_ulong();
276 // We cannot have a zero enumeration name declaration count.
277 if (! zero_ok && (value == 0)) {
278 yyerror(loc, "error: zero count used in enum name sequence.");
285 static void current_task_set_statement(const YYLTYPE&loc, vector<Statement*>*s)
288 /* if the statement list is null, then the parser
289 detected the case that there are no statements in the
290 task. If this is SystemVerilog, handle it as an
292 if (!gn_system_verilog()) {
293 yyerror(loc, "error: Support for empty tasks requires SystemVerilog.");
295 PBlock*tmp = new PBlock(PBlock::BL_SEQ);
297 current_task->set_statement(tmp);
302 /* An empty vector represents one or more null statements. Handle
303 this as a simple null statement. */
307 /* A vector of 1 is handled as a simple statement. */
308 if (s->size() == 1) {
309 current_task->set_statement((*s)[0]);
313 if (!gn_system_verilog()) {
314 yyerror(loc, "error: Task body with multiple statements requires SystemVerilog.");
317 PBlock*tmp = new PBlock(PBlock::BL_SEQ);
319 tmp->set_statement(*s);
320 current_task->set_statement(tmp);
323 static void current_function_set_statement(const YYLTYPE&loc, vector<Statement*>*s)
326 /* if the statement list is null, then the parser
327 detected the case that there are no statements in the
328 task. If this is SystemVerilog, handle it as an
330 if (!gn_system_verilog()) {
331 yyerror(loc, "error: Support for empty functions requires SystemVerilog.");
333 PBlock*tmp = new PBlock(PBlock::BL_SEQ);
335 current_function->set_statement(tmp);
340 /* An empty vector represents one or more null statements. Handle
341 this as a simple null statement. */
345 /* A vector of 1 is handled as a simple statement. */
346 if (s->size() == 1) {
347 current_function->set_statement((*s)[0]);
351 if (!gn_system_verilog()) {
352 yyerror(loc, "error: Function body with multiple statements requires SystemVerilog.");
355 PBlock*tmp = new PBlock(PBlock::BL_SEQ);
357 tmp->set_statement(*s);
358 current_function->set_statement(tmp);
369 /* text items are C strings allocated by the lexor using
370 strdup. They can be put into lists with the texts type. */
372 list<perm_string>*perm_strings;
374 list<pform_port_t>*port_list;
376 vector<pform_tf_port_t>* tf_ports;
378 pform_name_t*pform_name;
380 ivl_discipline_t discipline;
384 list<string>*strings;
386 struct str_pair_t drive;
389 svector<PCase::Item*>*citems;
392 svector<lgate>*gates;
394 Module::port_t *mport;
395 LexicalScope::range_t* value_range;
396 vector<Module::port_t*>*mports;
398 named_number_t* named_number;
399 list<named_number_t>* named_numbers;
401 named_pexpr_t*named_pexpr;
402 list<named_pexpr_t>*named_pexprs;
403 struct parmvalue_t*parmvalue;
404 list<pform_range_t>*ranges;
409 svector<PEEvent*>*event_expr;
411 NetNet::Type nettype;
412 PGBuiltin::Type gatetype;
413 NetNet::PortType porttype;
414 ivl_variable_type_t vartype;
415 PBlock::BL_TYPE join_keyword;
418 vector<PWire*>*wires;
420 PEventStatement*event_statement;
422 vector<Statement*>*statement_list;
424 net_decl_assign_t*net_decl_assign;
425 enum_type_t*enum_type;
427 decl_assignment_t*decl_assignment;
428 list<decl_assignment_t*>*decl_assignments;
430 struct_member_t*struct_member;
431 list<struct_member_t*>*struct_members;
432 struct_type_t*struct_type;
434 data_type_t*data_type;
435 class_type_t*class_type;
436 real_type_t::type_t real_type;
437 property_qualifier_t property_qualifier;
448 } class_declaration_extends;
455 list<index_component_t> *dimensions;
457 LexicalScope::lifetime_t lifetime;
460 %token <text> IDENTIFIER SYSTEM_IDENTIFIER STRING TIME_LITERAL
461 %token <type_identifier> TYPE_IDENTIFIER
462 %token <package> PACKAGE_IDENTIFIER
463 %token <discipline> DISCIPLINE_IDENTIFIER
464 %token <text> PATHPULSE_IDENTIFIER
465 %token <number> BASED_NUMBER DEC_NUMBER UNBASED_NUMBER
466 %token <realtime> REALTIME
467 %token K_PLUS_EQ K_MINUS_EQ K_INCR K_DECR
468 %token K_LE K_GE K_EG K_EQ K_NE K_CEQ K_CNE K_WEQ K_WNE K_LP K_LS K_RS K_RSS K_SG
469 /* K_CONTRIBUTE is <+, the contribution assign. */
471 %token K_PO_POS K_PO_NEG K_POW
472 %token K_PSTAR K_STARP K_DOTSTAR
473 %token K_LOR K_LAND K_NAND K_NOR K_NXOR K_TRIGGER
475 %token K_edge_descriptor
477 /* The base tokens from 1364-1995. */
478 %token K_always K_and K_assign K_begin K_buf K_bufif0 K_bufif1 K_case
479 %token K_casex K_casez K_cmos K_deassign K_default K_defparam K_disable
480 %token K_edge K_else K_end K_endcase K_endfunction K_endmodule
481 %token K_endprimitive K_endspecify K_endtable K_endtask K_event K_for
482 %token K_force K_forever K_fork K_function K_highz0 K_highz1 K_if
483 %token K_ifnone K_initial K_inout K_input K_integer K_join K_large
484 %token K_macromodule K_medium K_module K_nand K_negedge K_nmos K_nor
485 %token K_not K_notif0 K_notif1 K_or K_output K_parameter K_pmos K_posedge
486 %token K_primitive K_pull0 K_pull1 K_pulldown K_pullup K_rcmos K_real
487 %token K_realtime K_reg K_release K_repeat K_rnmos K_rpmos K_rtran
488 %token K_rtranif0 K_rtranif1 K_scalared K_small K_specify K_specparam
489 %token K_strong0 K_strong1 K_supply0 K_supply1 K_table K_task K_time
490 %token K_tran K_tranif0 K_tranif1 K_tri K_tri0 K_tri1 K_triand K_trior
491 %token K_trireg K_vectored K_wait K_wand K_weak0 K_weak1 K_while K_wire
492 %token K_wor K_xnor K_xor
494 %token K_Shold K_Snochange K_Speriod K_Srecovery K_Ssetup K_Ssetuphold
495 %token K_Sskew K_Swidth
497 /* Icarus specific tokens. */
498 %token KK_attribute K_bool K_logic
500 /* The new tokens from 1364-2001. */
501 %token K_automatic K_endgenerate K_generate K_genvar K_localparam
502 %token K_noshowcancelled K_pulsestyle_onevent K_pulsestyle_ondetect
503 %token K_showcancelled K_signed K_unsigned
505 %token K_Sfullskew K_Srecrem K_Sremoval K_Stimeskew
507 /* The 1364-2001 configuration tokens. */
508 %token K_cell K_config K_design K_endconfig K_incdir K_include K_instance
509 %token K_liblist K_library K_use
511 /* The new tokens from 1364-2005. */
512 %token K_wone K_uwire
514 /* The new tokens from 1800-2005. */
515 %token K_alias K_always_comb K_always_ff K_always_latch K_assert
516 %token K_assume K_before K_bind K_bins K_binsof K_bit K_break K_byte
517 %token K_chandle K_class K_clocking K_const K_constraint K_context
518 %token K_continue K_cover K_covergroup K_coverpoint K_cross K_dist K_do
519 %token K_endclass K_endclocking K_endgroup K_endinterface K_endpackage
520 %token K_endprogram K_endproperty K_endsequence K_enum K_expect K_export
521 %token K_extends K_extern K_final K_first_match K_foreach K_forkjoin
522 %token K_iff K_ignore_bins K_illegal_bins K_import K_inside K_int
523 /* Icarus already has defined "logic" above! */
524 %token K_interface K_intersect K_join_any K_join_none K_local
525 %token K_longint K_matches K_modport K_new K_null K_package K_packed
526 %token K_priority K_program K_property K_protected K_pure K_rand K_randc
527 %token K_randcase K_randsequence K_ref K_return K_sequence K_shortint
528 %token K_shortreal K_solve K_static K_string K_struct K_super
529 %token K_tagged K_this K_throughout K_timeprecision K_timeunit K_type
530 %token K_typedef K_union K_unique K_var K_virtual K_void K_wait_order
531 %token K_wildcard K_with K_within
533 /* The new tokens from 1800-2009. */
534 %token K_accept_on K_checker K_endchecker K_eventually K_global K_implies
535 %token K_let K_nexttime K_reject_on K_restrict K_s_always K_s_eventually
536 %token K_s_nexttime K_s_until K_s_until_with K_strong K_sync_accept_on
537 %token K_sync_reject_on K_unique0 K_until K_until_with K_untyped K_weak
539 /* The new tokens from 1800-2012. */
540 %token K_implements K_interconnect K_nettype K_soft
542 /* The new tokens for Verilog-AMS 2.3. */
543 %token K_above K_abs K_absdelay K_abstol K_access K_acos K_acosh
544 /* 1800-2005 has defined "assert" above! */
545 %token K_ac_stim K_aliasparam K_analog K_analysis K_asin K_asinh
546 %token K_atan K_atan2 K_atanh K_branch K_ceil K_connect K_connectmodule
547 %token K_connectrules K_continuous K_cos K_cosh K_ddt K_ddt_nature K_ddx
548 %token K_discipline K_discrete K_domain K_driver_update K_endconnectrules
549 %token K_enddiscipline K_endnature K_endparamset K_exclude K_exp
550 %token K_final_step K_flicker_noise K_floor K_flow K_from K_ground
551 %token K_hypot K_idt K_idtmod K_idt_nature K_inf K_initial_step
552 %token K_laplace_nd K_laplace_np K_laplace_zd K_laplace_zp
553 %token K_last_crossing K_limexp K_ln K_log K_max K_merged K_min K_nature
554 %token K_net_resolution K_noise_table K_paramset K_potential K_pow
555 /* 1800-2005 has defined "string" above! */
556 %token K_resolveto K_sin K_sinh K_slew K_split K_sqrt K_tan K_tanh
557 %token K_timer K_transition K_units K_white_noise K_wreal
558 %token K_zi_nd K_zi_np K_zi_zd K_zi_zp
560 %type <flag> from_exclude block_item_decls_opt
561 %type <number> number pos_neg_number
562 %type <flag> signing unsigned_signed_opt signed_unsigned_opt
563 %type <flag> import_export
564 %type <flag> K_packed_opt K_reg_opt K_static_opt K_virtual_opt
565 %type <flag> udp_reg_opt edge_operator
566 %type <drive> drive_strength drive_strength_opt dr_strength0 dr_strength1
567 %type <letter> udp_input_sym udp_output_sym
568 %type <text> udp_input_list udp_sequ_entry udp_comb_entry
569 %type <perm_strings> udp_input_declaration_list
570 %type <strings> udp_entry_list udp_comb_entry_list udp_sequ_entry_list
571 %type <strings> udp_body
572 %type <perm_strings> udp_port_list
573 %type <wires> udp_port_decl udp_port_decls
574 %type <statement> udp_initial udp_init_opt
575 %type <expr> udp_initial_expr_opt
577 %type <text> register_variable net_variable event_variable endlabel_opt class_declaration_endlabel_opt
578 %type <perm_strings> register_variable_list net_variable_list event_variable_list
579 %type <perm_strings> list_of_identifiers loop_variables
580 %type <port_list> list_of_port_identifiers list_of_variable_port_identifiers
582 %type <net_decl_assign> net_decl_assign net_decl_assigns
584 %type <mport> port port_opt port_reference port_reference_list
585 %type <mport> port_declaration
586 %type <mports> list_of_ports module_port_list_opt list_of_port_declarations module_attribute_foreign
587 %type <value_range> parameter_value_range parameter_value_ranges
588 %type <value_range> parameter_value_ranges_opt
589 %type <expr> tf_port_item_expr_opt value_range_expression
591 %type <named_pexprs> enum_name_list enum_name
592 %type <enum_type> enum_data_type
594 %type <tf_ports> function_item function_item_list function_item_list_opt
595 %type <tf_ports> task_item task_item_list task_item_list_opt
596 %type <tf_ports> tf_port_declaration tf_port_item tf_port_item_list tf_port_list tf_port_list_opt
598 %type <named_pexpr> modport_simple_port port_name parameter_value_byname
599 %type <named_pexprs> port_name_list parameter_value_byname_list
601 %type <named_pexpr> attribute
602 %type <named_pexprs> attribute_list attribute_instance_list attribute_list_opt
604 %type <citem> case_item
605 %type <citems> case_items
607 %type <gate> gate_instance
608 %type <gates> gate_instance_list
610 %type <pform_name> hierarchy_identifier implicit_class_handle
611 %type <expr> assignment_pattern expression expr_mintypmax
612 %type <expr> expr_primary_or_typename expr_primary
613 %type <expr> class_new dynamic_array_new
614 %type <expr> inc_or_dec_expression inside_expression lpvalue
615 %type <expr> branch_probe_expression streaming_concatenation
616 %type <expr> delay_value delay_value_simple
617 %type <exprs> delay1 delay3 delay3_opt delay_value_list
618 %type <exprs> expression_list_with_nuls expression_list_proper
619 %type <exprs> cont_assign cont_assign_list
621 %type <decl_assignment> variable_decl_assignment
622 %type <decl_assignments> list_of_variable_decl_assignments
624 %type <data_type> data_type data_type_or_implicit data_type_or_implicit_or_void
625 %type <data_type> simple_type_or_string
626 %type <class_type> class_identifier
627 %type <struct_member> struct_union_member
628 %type <struct_members> struct_union_member_list
629 %type <struct_type> struct_data_type
631 %type <class_declaration_extends> class_declaration_extends_opt
633 %type <property_qualifier> class_item_qualifier property_qualifier
634 %type <property_qualifier> class_item_qualifier_list property_qualifier_list
635 %type <property_qualifier> class_item_qualifier_opt property_qualifier_opt
636 %type <property_qualifier> random_qualifier
638 %type <ranges> variable_dimension
639 %type <ranges> dimensions_opt dimensions
641 %type <nettype> net_type net_type_opt
642 %type <gatetype> gatetype switchtype
643 %type <porttype> port_direction port_direction_opt
644 %type <vartype> bit_logic bit_logic_opt
645 %type <vartype> integer_vector_type
646 %type <parmvalue> parameter_value_opt
648 %type <event_expr> event_expression_list
649 %type <event_expr> event_expression
650 %type <event_statement> event_control
651 %type <statement> statement statement_item statement_or_null
652 %type <statement> compressed_statement
653 %type <statement> loop_statement for_step jump_statement
654 %type <statement> procedural_assertion_statement
655 %type <statement_list> statement_or_null_list statement_or_null_list_opt
657 %type <statement> analog_statement
659 %type <join_keyword> join_keyword
661 %type <letter> spec_polarity
662 %type <perm_strings> specify_path_identifiers
664 %type <specpath> specify_simple_path specify_simple_path_decl
665 %type <specpath> specify_edge_path specify_edge_path_decl
667 %type <real_type> non_integer_type
668 %type <int_val> atom2_type
669 %type <int_val> module_start module_end
671 %type <lifetime> lifetime lifetime_opt
674 %right K_PLUS_EQ K_MINUS_EQ K_MUL_EQ K_DIV_EQ K_MOD_EQ K_AND_EQ K_OR_EQ
675 %right K_XOR_EQ K_LS_EQ K_RS_EQ K_RSS_EQ
676 %right '?' ':' K_inside
680 %left '^' K_NXOR K_NOR
682 %left K_EQ K_NE K_CEQ K_CNE K_WEQ K_WNE
683 %left K_GE K_LE '<' '>'
684 %left K_LS K_RS K_RSS
691 /* to resolve dangling else ambiguity. */
692 %nonassoc less_than_K_else
695 /* to resolve exclude (... ambiguity */
699 /* to resolve timeunits declaration/redeclaration ambiguity */
700 %nonassoc no_timeunits_declaration
701 %nonassoc one_timeunits_declaration
702 %nonassoc K_timeunit K_timeprecision
707 /* IEEE1800-2005: A.1.2 */
708 /* source_text ::= [ timeunits_declaration ] { description } */
710 : timeunits_declaration_opt
711 { pform_set_scope_timescale(yyloc); }
716 assertion_item /* IEEE1800-2012: A.6.10 */
717 : concurrent_assertion_item
720 assignment_pattern /* IEEE1800-2005: A.6.7.1 */
721 : K_LP expression_list_proper '}'
722 { PEAssignPattern*tmp = new PEAssignPattern(*$2);
728 { PEAssignPattern*tmp = new PEAssignPattern;
734 /* Some rules have a ... [ block_identifier ':' ] ... part. This
735 implements it in a LALR way. */
736 block_identifier_opt /* */
741 class_declaration /* IEEE1800-2005: A.1.2 */
742 : K_virtual_opt K_class lifetime_opt class_identifier class_declaration_extends_opt ';'
743 { pform_start_class_declaration(@2, $4, $5.type, $5.exprs, $3); }
744 class_items_opt K_endclass
745 { // Process a class.
746 pform_end_class_declaration(@9);
748 class_declaration_endlabel_opt
749 { // Wrap up the class.
750 if ($11 && $4 && $4->name != $11) {
751 yyerror(@11, "error: Class end label doesn't match class name.");
757 class_constraint /* IEEE1800-2005: A.1.8 */
758 : constraint_prototype
759 | constraint_declaration
764 { // Create a synthetic typedef for the class name so that the
765 // lexor detects the name as a type.
766 perm_string name = lex_strings.make($1);
767 class_type_t*tmp = new class_type_t(name);
769 pform_set_typedef(name, tmp, NULL);
774 { class_type_t*tmp = dynamic_cast<class_type_t*>($1.type);
776 yyerror(@1, "Type name \"%s\"is not a predeclared class name.", $1.text);
783 /* The endlabel after a class declaration is a little tricky because
784 the class name is detected by the lexor as a TYPE_IDENTIFIER if it
785 does indeed match a name. */
786 class_declaration_endlabel_opt
787 : ':' TYPE_IDENTIFIER
788 { class_type_t*tmp = dynamic_cast<class_type_t*> ($2.type);
790 yyerror(@2, "error: class declaration endlabel \"%s\" is not a class name\n", $2.text);
793 $$ = strdupnew(tmp->name.str());
803 /* This rule implements [ extends class_type ] in the
804 class_declaration. It is not a rule of its own in the LRM.
806 Note that for this to be correct, the identifier after the
807 extends keyword must be a class name. Therefore, match
808 TYPE_IDENTIFIER instead of IDENTIFIER, and this rule will return
811 class_declaration_extends_opt /* IEEE1800-2005: A.1.2 */
812 : K_extends TYPE_IDENTIFIER
817 | K_extends TYPE_IDENTIFIER '(' expression_list_with_nuls ')'
823 { $$.type = 0; $$.exprs = 0; }
826 /* The class_items_opt and class_items rules together implement the
827 rule snippet { class_item } (zero or more class_item) of the
828 class_declaration. */
829 class_items_opt /* IEEE1800-2005: A.1.2 */
834 class_items /* IEEE1800-2005: A.1.2 */
835 : class_items class_item
839 class_item /* IEEE1800-2005: A.1.8 */
841 /* IEEE1800 A.1.8: class_constructor_declaration */
842 : method_qualifier_opt K_function K_new
843 { assert(current_function==0);
844 current_function = pform_push_constructor_scope(@3);
846 '(' tf_port_list_opt ')' ';'
847 function_item_list_opt
848 statement_or_null_list_opt
849 K_endfunction endnew_opt
850 { current_function->set_ports($6);
851 pform_set_constructor_return(current_function);
852 pform_set_this_class(@3, current_function);
853 current_function_set_statement(@3, $10);
855 current_function = 0;
858 /* Class properties... */
860 | property_qualifier_opt data_type list_of_variable_decl_assignments ';'
861 { pform_class_property(@2, $1, $2, $3); }
863 | K_const class_item_qualifier_opt data_type list_of_variable_decl_assignments ';'
864 { pform_class_property(@1, $2 | property_qualifier_t::make_const(), $3, $4); }
866 /* Class methods... */
868 | method_qualifier_opt task_declaration
869 { /* The task_declaration rule puts this into the class */ }
871 | method_qualifier_opt function_declaration
872 { /* The function_declaration rule puts this into the class */ }
874 /* External class method definitions... */
876 | K_extern method_qualifier_opt K_function K_new ';'
877 { yyerror(@1, "sorry: External constructors are not yet supported."); }
878 | K_extern method_qualifier_opt K_function K_new '(' tf_port_list_opt ')' ';'
879 { yyerror(@1, "sorry: External constructors are not yet supported."); }
880 | K_extern method_qualifier_opt K_function data_type_or_implicit_or_void
882 { yyerror(@1, "sorry: External methods are not yet supported.");
885 | K_extern method_qualifier_opt K_function data_type_or_implicit_or_void
886 IDENTIFIER '(' tf_port_list_opt ')' ';'
887 { yyerror(@1, "sorry: External methods are not yet supported.");
890 | K_extern method_qualifier_opt K_task IDENTIFIER ';'
891 { yyerror(@1, "sorry: External methods are not yet supported.");
894 | K_extern method_qualifier_opt K_task IDENTIFIER '(' tf_port_list_opt ')' ';'
895 { yyerror(@1, "sorry: External methods are not yet supported.");
899 /* Class constraints... */
903 /* Here are some error matching rules to help recover from various
904 syntax errors within a class declaration. */
906 | property_qualifier_opt data_type error ';'
907 { yyerror(@3, "error: Errors in variable names after data type.");
911 | property_qualifier_opt IDENTIFIER error ';'
912 { yyerror(@3, "error: %s doesn't name a type.", $2);
916 | method_qualifier_opt K_function K_new error K_endfunction endnew_opt
917 { yyerror(@1, "error: I give up on this class constructor declaration.");
922 { yyerror(@2, "error: invalid class item.");
928 class_item_qualifier /* IEEE1800-2005 A.1.8 */
929 : K_static { $$ = property_qualifier_t::make_static(); }
930 | K_protected { $$ = property_qualifier_t::make_protected(); }
931 | K_local { $$ = property_qualifier_t::make_local(); }
934 class_item_qualifier_list
935 : class_item_qualifier_list class_item_qualifier { $$ = $1 | $2; }
936 | class_item_qualifier { $$ = $1; }
939 class_item_qualifier_opt
940 : class_item_qualifier_list { $$ = $1; }
941 | { $$ = property_qualifier_t::make_none(); }
944 class_new /* IEEE1800-2005 A.2.4 */
945 : K_new '(' expression_list_with_nuls ')'
946 { list<PExpr*>*expr_list = $3;
947 strip_tail_items(expr_list);
948 PENewClass*tmp = new PENewClass(*expr_list);
953 | K_new hierarchy_identifier
954 { PEIdent*tmpi = new PEIdent(*$2);
956 PENewCopy*tmp = new PENewCopy(tmpi);
962 { PENewClass*tmp = new PENewClass;
968 /* The concurrent_assertion_item pulls together the
969 concurrent_assertion_statement and checker_instantiation rules. */
971 concurrent_assertion_item /* IEEE1800-2012 A.2.10 */
972 : block_identifier_opt K_assert K_property '(' property_spec ')' statement_or_null
974 if (gn_assertions_flag) {
975 yyerror(@2, "sorry: concurrent_assertion_item not supported."
976 " Try -gno-assertion to turn this message off.");
979 | block_identifier_opt K_assert K_property '(' error ')' statement_or_null
981 yyerror(@2, "error: Error in property_spec of concurrent assertion item.");
985 constraint_block_item /* IEEE1800-2005 A.1.9 */
986 : constraint_expression
989 constraint_block_item_list
990 : constraint_block_item_list constraint_block_item
991 | constraint_block_item
994 constraint_block_item_list_opt
996 | constraint_block_item_list
999 constraint_declaration /* IEEE1800-2005: A.1.9 */
1000 : K_static_opt K_constraint IDENTIFIER '{' constraint_block_item_list_opt '}'
1001 { yyerror(@2, "sorry: Constraint declarations not supported."); }
1003 /* Error handling rules... */
1005 | K_static_opt K_constraint IDENTIFIER '{' error '}'
1006 { yyerror(@4, "error: Errors in the constraint block item list."); }
1009 constraint_expression /* IEEE1800-2005 A.1.9 */
1011 | expression K_dist '{' '}' ';'
1012 | expression K_TRIGGER constraint_set
1013 | K_if '(' expression ')' constraint_set %prec less_than_K_else
1014 | K_if '(' expression ')' constraint_set K_else constraint_set
1015 | K_foreach '(' IDENTIFIER '[' loop_variables ']' ')' constraint_set
1018 constraint_expression_list /* */
1019 : constraint_expression_list constraint_expression
1020 | constraint_expression
1023 constraint_prototype /* IEEE1800-2005: A.1.9 */
1024 : K_static_opt K_constraint IDENTIFIER ';'
1025 { yyerror(@2, "sorry: Constraint prototypes not supported."); }
1028 constraint_set /* IEEE1800-2005 A.1.9 */
1029 : constraint_expression
1030 | '{' constraint_expression_list '}'
1033 data_declaration /* IEEE1800-2005: A.2.1.3 */
1034 : attribute_list_opt data_type_or_implicit list_of_variable_decl_assignments ';'
1035 { data_type_t*data_type = $2;
1036 if (data_type == 0) {
1037 data_type = new vector_type_t(IVL_VT_LOGIC, false, 0);
1038 FILE_NAME(data_type, @2);
1040 pform_makewire(@2, 0, str_strength, $3, NetNet::IMPLICIT_REG, data_type);
1044 data_type /* IEEE1800-2005: A.2.2.1 */
1045 : integer_vector_type unsigned_signed_opt dimensions_opt
1046 { ivl_variable_type_t use_vtype = $1;
1047 bool reg_flag = false;
1048 if (use_vtype == IVL_VT_NO_TYPE) {
1049 use_vtype = IVL_VT_LOGIC;
1052 vector_type_t*tmp = new vector_type_t(use_vtype, $2, $3);
1053 tmp->reg_flag = reg_flag;
1058 { real_type_t*tmp = new real_type_t($1);
1063 { if (!$1->packed_flag) {
1064 yyerror(@1, "sorry: Unpacked structs not supported.");
1070 | atom2_type signed_unsigned_opt
1071 { atom2_type_t*tmp = new atom2_type_t($1, $2);
1075 | K_integer signed_unsigned_opt
1076 { list<pform_range_t>*pd = make_range_from_width(integer_width);
1077 vector_type_t*tmp = new vector_type_t(IVL_VT_LOGIC, $2, pd);
1078 tmp->reg_flag = true;
1079 tmp->integer_flag = true;
1083 { list<pform_range_t>*pd = make_range_from_width(64);
1084 vector_type_t*tmp = new vector_type_t(IVL_VT_LOGIC, false, pd);
1085 tmp->reg_flag = !gn_system_verilog();
1088 | TYPE_IDENTIFIER dimensions_opt
1090 parray_type_t*tmp = new parray_type_t($1.type, $2);
1093 } else $$ = $1.type;
1096 | PACKAGE_IDENTIFIER K_SCOPE_RES
1097 { lex_in_package_scope($1); }
1099 { lex_in_package_scope(0);
1104 { string_type_t*tmp = new string_type_t;
1110 /* The data_type_or_implicit rule is a little more complex then the
1111 rule documented in the IEEE format syntax in order to allow for
1112 signaling the special case that the data_type is completely
1113 absent. The context may need that information to decide to resort
1116 data_type_or_implicit /* IEEE1800-2005: A.2.2.1 */
1119 | signing dimensions_opt
1120 { vector_type_t*tmp = new vector_type_t(IVL_VT_LOGIC, $1, $2);
1121 tmp->implicit_flag = true;
1126 { vector_type_t*tmp = new vector_type_t(IVL_VT_LOGIC, false, $1);
1127 tmp->implicit_flag = true;
1136 data_type_or_implicit_or_void
1137 : data_type_or_implicit
1140 { void_type_t*tmp = new void_type_t;
1146 /* NOTE: The "module" rule of the description combines the
1147 module_declaration, program_declaration, and interface_declaration
1148 rules from the standard description. */
1150 description /* IEEE1800-2005: A.1.2 */
1153 | config_declaration
1154 | nature_declaration
1155 | package_declaration
1156 | discipline_declaration
1158 | KK_attribute '(' IDENTIFIER ',' STRING ',' STRING ')'
1159 { perm_string tmp3 = lex_strings.make($3);
1160 pform_set_type_attrib(tmp3, $5, $7);
1168 | description_list description
1172 /* This implements the [ : IDENTIFIER ] part of the constructor
1173 rule documented in IEEE1800-2005: A.1.8 */
1174 endnew_opt : ':' K_new | ;
1176 /* The dynamic_array_new rule is kinda like an expression, but it is
1177 treated differently by rules that use this "expression". Watch out! */
1179 dynamic_array_new /* IEEE1800-2005: A.2.4 */
1180 : K_new '[' expression ']'
1181 { $$ = new PENewArray($3, 0);
1184 | K_new '[' expression ']' '(' expression ')'
1185 { $$ = new PENewArray($3, $6);
1190 for_step /* IEEE1800-2005: A.6.8 */
1191 : lpvalue '=' expression
1192 { PAssign*tmp = new PAssign($1,$3);
1196 | inc_or_dec_expression
1197 { $$ = pform_compressed_assign_from_inc_dec(@1, $1); }
1198 | compressed_statement
1203 /* The function declaration rule matches the function declaration
1204 header, then pushes the function scope. This causes the
1205 definitions in the func_body to take on the scope of the function
1206 instead of the module. */
1207 function_declaration /* IEEE1800-2005: A.2.6 */
1208 : K_function lifetime_opt data_type_or_implicit_or_void IDENTIFIER ';'
1209 { assert(current_function == 0);
1210 current_function = pform_push_function_scope(@1, $4, $2);
1212 function_item_list statement_or_null_list_opt
1214 { current_function->set_ports($7);
1215 current_function->set_return($3);
1216 current_function_set_statement($8? @8 : @4, $8);
1217 pform_set_this_class(@4, current_function);
1219 current_function = 0;
1222 { // Last step: check any closing name.
1224 if (strcmp($4,$11) != 0) {
1225 yyerror(@11, "error: End label doesn't match "
1228 if (! gn_system_verilog()) {
1229 yyerror(@11, "error: Function end labels require "
1237 | K_function lifetime_opt data_type_or_implicit_or_void IDENTIFIER
1238 { assert(current_function == 0);
1239 current_function = pform_push_function_scope(@1, $4, $2);
1241 '(' tf_port_list_opt ')' ';'
1242 block_item_decls_opt
1243 statement_or_null_list_opt
1245 { current_function->set_ports($7);
1246 current_function->set_return($3);
1247 current_function_set_statement($11? @11 : @4, $11);
1248 pform_set_this_class(@4, current_function);
1250 current_function = 0;
1251 if ($7==0 && !gn_system_verilog()) {
1252 yyerror(@4, "error: Empty parenthesis syntax requires SystemVerilog.");
1256 { // Last step: check any closing name.
1258 if (strcmp($4,$14) != 0) {
1259 yyerror(@14, "error: End label doesn't match "
1262 if (! gn_system_verilog()) {
1263 yyerror(@14, "error: Function end labels require "
1271 /* Detect and recover from some errors. */
1273 | K_function lifetime_opt data_type_or_implicit_or_void IDENTIFIER error K_endfunction
1275 if (current_function) {
1277 current_function = 0;
1279 assert(current_function == 0);
1280 yyerror(@1, "error: Syntax error defining function.");
1284 { // Last step: check any closing name.
1286 if (strcmp($4,$8) != 0) {
1287 yyerror(@8, "error: End label doesn't match function name");
1289 if (! gn_system_verilog()) {
1290 yyerror(@8, "error: Function end labels require "
1300 import_export /* IEEE1800-2012: A.2.9 */
1301 : K_import { $$ = true; }
1302 | K_export { $$ = false; }
1305 implicit_class_handle /* IEEE1800-2005: A.8.4 */
1306 : K_this { $$ = pform_create_this(); }
1307 | K_super { $$ = pform_create_super(); }
1310 /* SystemVerilog adds support for the increment/decrement
1311 expressions, which look like a++, --a, etc. These are primaries
1312 but are in their own rules because they can also be
1313 statements. Note that the operator can only take l-value
1316 inc_or_dec_expression /* IEEE1800-2005: A.4.3 */
1317 : K_INCR lpvalue %prec UNARY_PREC
1318 { PEUnary*tmp = new PEUnary('I', $2);
1322 | lpvalue K_INCR %prec UNARY_PREC
1323 { PEUnary*tmp = new PEUnary('i', $1);
1327 | K_DECR lpvalue %prec UNARY_PREC
1328 { PEUnary*tmp = new PEUnary('D', $2);
1332 | lpvalue K_DECR %prec UNARY_PREC
1333 { PEUnary*tmp = new PEUnary('d', $1);
1339 inside_expression /* IEEE1800-2005 A.8.3 */
1340 : expression K_inside '{' open_range_list '}'
1341 { yyerror(@2, "sorry: \"inside\" expressions not supported yet.");
1346 integer_vector_type /* IEEE1800-2005: A.2.2.1 */
1347 : K_reg { $$ = IVL_VT_NO_TYPE; } /* Usually a synonym for logic. */
1348 | K_bit { $$ = IVL_VT_BOOL; }
1349 | K_logic { $$ = IVL_VT_LOGIC; }
1350 | K_bool { $$ = IVL_VT_BOOL; } /* Icarus Verilog xtypes extension */
1353 join_keyword /* IEEE1800-2005: A.6.3 */
1355 { $$ = PBlock::BL_PAR; }
1357 { $$ = PBlock::BL_JOIN_NONE; }
1359 { $$ = PBlock::BL_JOIN_ANY; }
1362 jump_statement /* IEEE1800-2005: A.6.5 */
1364 { yyerror(@1, "sorry: break statements not supported.");
1368 { PReturn*tmp = new PReturn(0);
1372 | K_return expression ';'
1373 { PReturn*tmp = new PReturn($2);
1379 lifetime /* IEEE1800-2005: A.2.1.3 */
1380 : K_automatic { $$ = LexicalScope::AUTOMATIC; }
1381 | K_static { $$ = LexicalScope::STATIC; }
1384 lifetime_opt /* IEEE1800-2005: A.2.1.3 */
1385 : lifetime { $$ = $1; }
1386 | { $$ = LexicalScope::INHERITED; }
1389 /* Loop statements are kinds of statements. */
1391 loop_statement /* IEEE1800-2005: A.6.8 */
1392 : K_for '(' lpvalue '=' expression ';' expression ';' for_step ')'
1394 { PForStatement*tmp = new PForStatement($3, $5, $7, $9, $11);
1399 // Handle for_variable_declaration syntax by wrapping the for(...)
1400 // statement in a synthetic named block. We can name the block
1401 // after the variable that we are creating, that identifier is
1402 // safe in the controlling scope.
1403 | K_for '(' data_type IDENTIFIER '=' expression ';' expression ';' for_step ')'
1404 { static unsigned for_counter = 0;
1405 char for_block_name [64];
1406 snprintf(for_block_name, sizeof for_block_name, "$ivl_for_loop%u", for_counter);
1408 PBlock*tmp = pform_push_block_scope(for_block_name, PBlock::BL_SEQ);
1410 current_block_stack.push(tmp);
1412 list<decl_assignment_t*>assign_list;
1413 decl_assignment_t*tmp_assign = new decl_assignment_t;
1414 tmp_assign->name = lex_strings.make($4);
1415 assign_list.push_back(tmp_assign);
1416 pform_makewire(@4, 0, str_strength, &assign_list, NetNet::REG, $3);
1419 { pform_name_t tmp_hident;
1420 tmp_hident.push_back(name_component_t(lex_strings.make($4)));
1422 PEIdent*tmp_ident = pform_new_ident(tmp_hident);
1423 FILE_NAME(tmp_ident, @4);
1425 PForStatement*tmp_for = new PForStatement(tmp_ident, $6, $8, $10, $13);
1426 FILE_NAME(tmp_for, @1);
1429 vector<Statement*>tmp_for_list (1);
1430 tmp_for_list[0] = tmp_for;
1431 PBlock*tmp_blk = current_block_stack.top();
1432 current_block_stack.pop();
1433 tmp_blk->set_statement(tmp_for_list);
1438 | K_forever statement_or_null
1439 { PForever*tmp = new PForever($2);
1444 | K_repeat '(' expression ')' statement_or_null
1445 { PRepeat*tmp = new PRepeat($3, $5);
1450 | K_while '(' expression ')' statement_or_null
1451 { PWhile*tmp = new PWhile($3, $5);
1456 | K_do statement_or_null K_while '(' expression ')' ';'
1457 { PDoWhile*tmp = new PDoWhile($5, $2);
1462 // When matching a foreach loop, implicitly create a named block
1463 // to hold the definitions for the index variables.
1464 | K_foreach '(' IDENTIFIER '[' loop_variables ']' ')'
1465 { static unsigned foreach_counter = 0;
1466 char for_block_name[64];
1467 snprintf(for_block_name, sizeof for_block_name, "$ivl_foreach%u", foreach_counter);
1468 foreach_counter += 1;
1470 PBlock*tmp = pform_push_block_scope(for_block_name, PBlock::BL_SEQ);
1472 current_block_stack.push(tmp);
1474 pform_make_foreach_declarations(@1, $5);
1477 { PForeach*tmp_for = pform_make_foreach(@1, $3, $5, $9);
1480 vector<Statement*>tmp_for_list(1);
1481 tmp_for_list[0] = tmp_for;
1482 PBlock*tmp_blk = current_block_stack.top();
1483 current_block_stack.pop();
1484 tmp_blk->set_statement(tmp_for_list);
1488 /* Error forms for loop statements. */
1490 | K_for '(' lpvalue '=' expression ';' expression ';' error ')'
1493 yyerror(@1, "error: Error in for loop step assignment.");
1496 | K_for '(' lpvalue '=' expression ';' error ';' for_step ')'
1499 yyerror(@1, "error: Error in for loop condition expression.");
1502 | K_for '(' error ')' statement_or_null
1504 yyerror(@1, "error: Incomprehensible for loop.");
1507 | K_while '(' error ')' statement_or_null
1509 yyerror(@1, "error: Error in while loop condition.");
1512 | K_do statement_or_null K_while '(' error ')' ';'
1514 yyerror(@1, "error: Error in do/while loop condition.");
1517 | K_foreach '(' IDENTIFIER '[' error ']' ')' statement_or_null
1519 yyerror(@4, "error: Errors in foreach loop variables list.");
1524 /* TODO: Replace register_variable_list with list_of_variable_decl_assignments. */
1525 list_of_variable_decl_assignments /* IEEE1800-2005 A.2.3 */
1526 : variable_decl_assignment
1527 { list<decl_assignment_t*>*tmp = new list<decl_assignment_t*>;
1531 | list_of_variable_decl_assignments ',' variable_decl_assignment
1532 { list<decl_assignment_t*>*tmp = $1;
1538 variable_decl_assignment /* IEEE1800-2005 A.2.3 */
1539 : IDENTIFIER dimensions_opt
1540 { decl_assignment_t*tmp = new decl_assignment_t;
1541 tmp->name = lex_strings.make($1);
1549 | IDENTIFIER '=' expression
1550 { decl_assignment_t*tmp = new decl_assignment_t;
1551 tmp->name = lex_strings.make($1);
1552 tmp->expr .reset($3);
1556 | IDENTIFIER '=' K_new '(' ')'
1557 { decl_assignment_t*tmp = new decl_assignment_t;
1558 tmp->name = lex_strings.make($1);
1559 PENewClass*expr = new PENewClass;
1560 FILE_NAME(expr, @3);
1561 tmp->expr .reset(expr);
1568 loop_variables /* IEEE1800-2005: A.6.8 */
1569 : loop_variables ',' IDENTIFIER
1570 { list<perm_string>*tmp = $1;
1571 tmp->push_back(lex_strings.make($3));
1576 { list<perm_string>*tmp = new list<perm_string>;
1577 tmp->push_back(lex_strings.make($1));
1583 method_qualifier /* IEEE1800-2005: A.1.8 */
1585 | class_item_qualifier
1588 method_qualifier_opt
1593 modport_declaration /* IEEE1800-2012: A.2.9 */
1595 { if (!pform_in_interface())
1596 yyerror(@1, "error: modport declarations are only allowed "
1599 modport_item_list ';'
1603 | modport_item_list ',' modport_item
1608 { pform_start_modport_item(@1, $1); }
1609 '(' modport_ports_list ')'
1610 { pform_end_modport_item(@1); }
1613 /* The modport_ports_list is a LALR(2) grammar. When the parser sees a
1614 ',' it needs to look ahead to the next token to decide whether it is
1615 a continuation of the preceding modport_ports_declaration, or the
1616 start of a new modport_ports_declaration. bison only supports LALR(1),
1617 so we have to handcraft a mini parser for this part of the syntax.
1618 last_modport_port holds the state for this mini parser.*/
1621 : modport_ports_declaration
1622 | modport_ports_list ',' modport_ports_declaration
1623 | modport_ports_list ',' modport_simple_port
1624 { if (last_modport_port.type == MP_SIMPLE) {
1625 pform_add_modport_port(@3, last_modport_port.direction,
1626 $3->name, $3->parm);
1628 yyerror(@3, "error: modport expression not allowed here.");
1632 | modport_ports_list ',' modport_tf_port
1633 { if (last_modport_port.type != MP_TF)
1634 yyerror(@3, "error: task/function declaration not allowed here.");
1636 | modport_ports_list ',' IDENTIFIER
1637 { if (last_modport_port.type == MP_SIMPLE) {
1638 pform_add_modport_port(@3, last_modport_port.direction,
1639 lex_strings.make($3), 0);
1640 } else if (last_modport_port.type != MP_TF) {
1641 yyerror(@3, "error: list of identifiers not allowed here.");
1645 | modport_ports_list ','
1646 { yyerror(@2, "error: NULL port declarations are not allowed"); }
1649 modport_ports_declaration
1650 : attribute_list_opt port_direction IDENTIFIER
1651 { last_modport_port.type = MP_SIMPLE;
1652 last_modport_port.direction = $2;
1653 pform_add_modport_port(@3, $2, lex_strings.make($3), 0);
1657 | attribute_list_opt port_direction modport_simple_port
1658 { last_modport_port.type = MP_SIMPLE;
1659 last_modport_port.direction = $2;
1660 pform_add_modport_port(@3, $2, $3->name, $3->parm);
1664 | attribute_list_opt import_export IDENTIFIER
1665 { last_modport_port.type = MP_TF;
1666 last_modport_port.is_import = $2;
1667 yyerror(@3, "sorry: modport task/function ports are not yet supported.");
1671 | attribute_list_opt import_export modport_tf_port
1672 { last_modport_port.type = MP_TF;
1673 last_modport_port.is_import = $2;
1674 yyerror(@3, "sorry: modport task/function ports are not yet supported.");
1677 | attribute_list_opt K_clocking IDENTIFIER
1678 { last_modport_port.type = MP_CLOCKING;
1679 last_modport_port.direction = NetNet::NOT_A_PORT;
1680 yyerror(@3, "sorry: modport clocking declaration is not yet supported.");
1687 : '.' IDENTIFIER '(' expression ')'
1688 { named_pexpr_t*tmp = new named_pexpr_t;
1689 tmp->name = lex_strings.make($2);
1698 | K_task IDENTIFIER '(' tf_port_list_opt ')'
1699 | K_function data_type_or_implicit_or_void IDENTIFIER
1700 | K_function data_type_or_implicit_or_void IDENTIFIER '(' tf_port_list_opt ')'
1703 non_integer_type /* IEEE1800-2005: A.2.2.1 */
1704 : K_real { $$ = real_type_t::REAL; }
1705 | K_realtime { $$ = real_type_t::REAL; }
1706 | K_shortreal { $$ = real_type_t::SHORTREAL; }
1709 number : BASED_NUMBER
1710 { $$ = $1; based_size = 0;}
1712 { $$ = $1; based_size = 0;}
1713 | DEC_NUMBER BASED_NUMBER
1714 { $$ = pform_verinum_with_size($1,$2, @2.text, @2.first_line);
1717 { $$ = $1; based_size = 0;}
1718 | DEC_NUMBER UNBASED_NUMBER
1719 { yyerror(@1, "error: Unbased SystemVerilog literal cannot have "
1721 $$ = $1; based_size = 0;}
1724 open_range_list /* IEEE1800-2005 A.2.11 */
1725 : open_range_list ',' value_range
1729 package_declaration /* IEEE1800-2005 A.1.2 */
1730 : K_package lifetime_opt IDENTIFIER ';'
1731 { pform_start_package_declaration(@1, $3, $2); }
1732 timeunits_declaration_opt
1733 { pform_set_scope_timescale(@1); }
1734 package_item_list_opt
1735 K_endpackage endlabel_opt
1736 { pform_end_package_declaration(@1);
1737 // If an end label is present make sure it match the package name.
1739 if (strcmp($3,$10) != 0) {
1740 yyerror(@10, "error: End label doesn't match package name");
1748 module_package_import_list_opt
1750 | package_import_list
1754 : package_import_declaration
1755 | package_import_list package_import_declaration
1758 package_import_declaration /* IEEE1800-2005 A.2.1.3 */
1759 : K_import package_import_item_list ';'
1764 : PACKAGE_IDENTIFIER K_SCOPE_RES IDENTIFIER
1765 { pform_package_import(@2, $1, $3);
1768 | PACKAGE_IDENTIFIER K_SCOPE_RES '*'
1769 { pform_package_import(@2, $1, 0);
1773 package_import_item_list
1774 : package_import_item_list',' package_import_item
1775 | package_import_item
1778 package_item /* IEEE1800-2005 A.1.10 */
1779 : timeunits_declaration
1780 | K_parameter param_type parameter_assign_list ';'
1781 | K_localparam param_type localparam_assign_list ';'
1783 | function_declaration
1790 : package_item_list package_item
1794 package_item_list_opt : package_item_list | ;
1796 port_direction /* IEEE1800-2005 A.1.3 */
1797 : K_input { $$ = NetNet::PINPUT; }
1798 | K_output { $$ = NetNet::POUTPUT; }
1799 | K_inout { $$ = NetNet::PINOUT; }
1801 { $$ = NetNet::PREF;
1802 if (!gn_system_verilog()) {
1803 yyerror(@1, "error: Reference ports (ref) require SystemVerilog.");
1804 $$ = NetNet::PINPUT;
1809 /* port_direction_opt is used in places where the port direction is
1810 optional. The default direction is selected by the context,
1811 which needs to notice the PIMPLICIT direction. */
1814 : port_direction { $$ = $1; }
1815 | { $$ = NetNet::PIMPLICIT; }
1818 property_expr /* IEEE1800-2012 A.2.10 */
1822 procedural_assertion_statement /* IEEE1800-2012 A.6.10 */
1823 : K_assert '(' expression ')' statement %prec less_than_K_else
1824 { yyerror(@1, "sorry: Simple immediate assertion statements not implemented.");
1827 | K_assert '(' expression ')' K_else statement
1828 { yyerror(@1, "sorry: Simple immediate assertion statements not implemented.");
1831 | K_assert '(' expression ')' statement K_else statement
1832 { yyerror(@1, "sorry: Simple immediate assertion statements not implemented.");
1837 /* The property_qualifier rule is as literally described in the LRM,
1838 but the use is usually as { property_qualifier }, which is
1839 implemented by the property_qualifier_opt rule below. */
1841 property_qualifier /* IEEE1800-2005 A.1.8 */
1842 : class_item_qualifier
1846 property_qualifier_opt /* IEEE1800-2005 A.1.8: ... { property_qualifier } */
1847 : property_qualifier_list { $$ = $1; }
1848 | { $$ = property_qualifier_t::make_none(); }
1851 property_qualifier_list /* IEEE1800-2005 A.1.8 */
1852 : property_qualifier_list property_qualifier { $$ = $1 | $2; }
1853 | property_qualifier { $$ = $1; }
1856 /* The property_spec rule uses some helper rules to implement this
1858 [ clocking_event ] [ disable iff ( expression_or_dist ) ] property_expr
1859 This does it is a YACC friendly way. */
1861 property_spec /* IEEE1800-2012 A.2.10 */
1862 : clocking_event_opt property_spec_disable_iff_opt property_expr
1865 property_spec_disable_iff_opt /* */
1866 : K_disable K_iff '(' expression ')'
1870 random_qualifier /* IEEE1800-2005 A.1.8 */
1871 : K_rand { $$ = property_qualifier_t::make_rand(); }
1872 | K_randc { $$ = property_qualifier_t::make_randc(); }
1875 /* real and realtime are exactly the same so save some code
1876 * with a common matching rule. */
1882 signing /* IEEE1800-2005: A.2.2.1 */
1883 : K_signed { $$ = true; }
1884 | K_unsigned { $$ = false; }
1887 simple_type_or_string /* IEEE1800-2005: A.2.2.1 */
1888 : integer_vector_type
1889 { ivl_variable_type_t use_vtype = $1;
1890 bool reg_flag = false;
1891 if (use_vtype == IVL_VT_NO_TYPE) {
1892 use_vtype = IVL_VT_LOGIC;
1895 vector_type_t*tmp = new vector_type_t(use_vtype, false, 0);
1896 tmp->reg_flag = reg_flag;
1901 { real_type_t*tmp = new real_type_t($1);
1906 { atom2_type_t*tmp = new atom2_type_t($1, true);
1911 { list<pform_range_t>*pd = make_range_from_width(integer_width);
1912 vector_type_t*tmp = new vector_type_t(IVL_VT_LOGIC, true, pd);
1913 tmp->reg_flag = true;
1914 tmp->integer_flag = true;
1918 { list<pform_range_t>*pd = make_range_from_width(64);
1919 vector_type_t*tmp = new vector_type_t(IVL_VT_LOGIC, false, pd);
1920 tmp->reg_flag = !gn_system_verilog();
1927 | PACKAGE_IDENTIFIER K_SCOPE_RES
1928 { lex_in_package_scope($1); }
1930 { lex_in_package_scope(0);
1935 { string_type_t*tmp = new string_type_t;
1941 statement /* IEEE1800-2005: A.6.4 */
1942 : attribute_list_opt statement_item
1943 { pform_bind_attributes($2->attributes, $1);
1948 /* Many places where statements are allowed can actually take a
1949 statement or a null statement marked with a naked semi-colon. */
1951 statement_or_null /* IEEE1800-2005: A.6.4 */
1954 | attribute_list_opt ';'
1962 stream_expression_list
1963 : stream_expression_list ',' stream_expression
1972 streaming_concatenation /* IEEE1800-2005: A.8.1 */
1973 : '{' stream_operator '{' stream_expression_list '}' '}'
1974 { /* streaming concatenation is a SystemVerilog thing. */
1975 if (gn_system_verilog()) {
1976 yyerror(@2, "sorry: Streaming concatenation not supported.");
1979 yyerror(@2, "error: Streaming concatenation requires SystemVerilog");
1985 /* The task declaration rule matches the task declaration
1986 header, then pushes the function scope. This causes the
1987 definitions in the task_body to take on the scope of the task
1988 instead of the module. */
1990 task_declaration /* IEEE1800-2005: A.2.7 */
1992 : K_task lifetime_opt IDENTIFIER ';'
1993 { assert(current_task == 0);
1994 current_task = pform_push_task_scope(@1, $3, $2);
1997 statement_or_null_list_opt
1999 { current_task->set_ports($6);
2000 current_task_set_statement(@3, $7);
2001 pform_set_this_class(@3, current_task);
2004 if ($7 && $7->size() > 1 && !gn_system_verilog()) {
2005 yyerror(@7, "error: Task body with multiple statements requires SystemVerilog.");
2010 { // Last step: check any closing name. This is done late so
2011 // that the parser can look ahead to detect the present
2012 // endlabel_opt but still have the pform_endmodule() called
2013 // early enough that the lexor can know we are outside the
2016 if (strcmp($3,$10) != 0) {
2017 yyerror(@10, "error: End label doesn't match task name");
2019 if (! gn_system_verilog()) {
2020 yyerror(@10, "error: Task end labels require "
2028 | K_task lifetime_opt IDENTIFIER '('
2029 { assert(current_task == 0);
2030 current_task = pform_push_task_scope(@1, $3, $2);
2032 tf_port_list ')' ';'
2033 block_item_decls_opt
2034 statement_or_null_list_opt
2036 { current_task->set_ports($6);
2037 current_task_set_statement(@3, $10);
2038 pform_set_this_class(@3, current_task);
2041 if ($10) delete $10;
2044 { // Last step: check any closing name. This is done late so
2045 // that the parser can look ahead to detect the present
2046 // endlabel_opt but still have the pform_endmodule() called
2047 // early enough that the lexor can know we are outside the
2050 if (strcmp($3,$13) != 0) {
2051 yyerror(@13, "error: End label doesn't match task name");
2053 if (! gn_system_verilog()) {
2054 yyerror(@13, "error: Task end labels require "
2062 | K_task lifetime_opt IDENTIFIER '(' ')' ';'
2063 { assert(current_task == 0);
2064 current_task = pform_push_task_scope(@1, $3, $2);
2066 block_item_decls_opt
2067 statement_or_null_list
2069 { current_task->set_ports(0);
2070 current_task_set_statement(@3, $9);
2071 pform_set_this_class(@3, current_task);
2072 if (! current_task->method_of()) {
2073 cerr << @3 << ": warning: task definition for \"" << $3
2074 << "\" has an empty port declaration list!" << endl;
2078 if ($9->size() > 1 && !gn_system_verilog()) {
2079 yyerror(@9, "error: Task body with multiple statements requires SystemVerilog.");
2084 { // Last step: check any closing name. This is done late so
2085 // that the parser can look ahead to detect the present
2086 // endlabel_opt but still have the pform_endmodule() called
2087 // early enough that the lexor can know we are outside the
2090 if (strcmp($3,$12) != 0) {
2091 yyerror(@12, "error: End label doesn't match task name");
2093 if (! gn_system_verilog()) {
2094 yyerror(@12, "error: Task end labels require "
2102 | K_task lifetime_opt IDENTIFIER error K_endtask
2110 { // Last step: check any closing name. This is done late so
2111 // that the parser can look ahead to detect the present
2112 // endlabel_opt but still have the pform_endmodule() called
2113 // early enough that the lexor can know we are outside the
2116 if (strcmp($3,$7) != 0) {
2117 yyerror(@7, "error: End label doesn't match task name");
2119 if (! gn_system_verilog()) {
2120 yyerror(@7, "error: Task end labels require "
2131 tf_port_declaration /* IEEE1800-2005: A.2.7 */
2132 : port_direction K_reg_opt unsigned_signed_opt dimensions_opt list_of_identifiers ';'
2133 { vector<pform_tf_port_t>*tmp = pform_make_task_ports(@1, $1,
2140 /* When the port is an integer, infer a signed vector of the integer
2141 shape. Generate a range ([31:0]) to make it work. */
2143 | port_direction K_integer list_of_identifiers ';'
2144 { list<pform_range_t>*range_stub = make_range_from_width(integer_width);
2145 vector<pform_tf_port_t>*tmp = pform_make_task_ports(@1, $1, IVL_VT_LOGIC, true,
2146 range_stub, $3, true);
2150 /* Ports can be time with a width of [63:0] (unsigned). */
2152 | port_direction K_time list_of_identifiers ';'
2153 { list<pform_range_t>*range_stub = make_range_from_width(64);
2154 vector<pform_tf_port_t>*tmp = pform_make_task_ports(@1, $1, IVL_VT_LOGIC, false,
2159 /* Ports can be real or realtime. */
2161 | port_direction real_or_realtime list_of_identifiers ';'
2162 { vector<pform_tf_port_t>*tmp = pform_make_task_ports(@1, $1, IVL_VT_REAL, true,
2168 /* Ports can be string. */
2170 | port_direction K_string list_of_identifiers ';'
2171 { vector<pform_tf_port_t>*tmp = pform_make_task_ports(@1, $1, IVL_VT_STRING, true,
2179 /* These rules for tf_port_item are slightly expanded from the
2180 strict rules in the LRM to help with LALR parsing.
2182 NOTE: Some of these rules should be folded into the "data_type"
2183 variant which uses the data_type rule to match data type
2184 declarations. That some rules do not use the data_type production
2185 is a consequence of legacy. */
2187 tf_port_item /* IEEE1800-2005: A.2.7 */
2189 : port_direction_opt data_type_or_implicit IDENTIFIER dimensions_opt tf_port_item_expr_opt
2190 { vector<pform_tf_port_t>*tmp;
2191 NetNet::PortType use_port_type = $1;
2192 if ((use_port_type == NetNet::PIMPLICIT) && (gn_system_verilog() || ($2 == 0)))
2193 use_port_type = port_declaration_context.port_type;
2194 perm_string name = lex_strings.make($3);
2195 list<perm_string>* ilist = list_from_identifier($3);
2197 if (use_port_type == NetNet::PIMPLICIT) {
2198 yyerror(@1, "error: missing task/function port direction.");
2199 use_port_type = NetNet::PINPUT; // for error recovery
2201 if (($2 == 0) && ($1==NetNet::PIMPLICIT)) {
2202 // Detect special case this is an undecorated
2203 // identifier and we need to get the declaration from
2206 yyerror(@4, "internal error: How can there be an unpacked range here?\n");
2208 tmp = pform_make_task_ports(@3, use_port_type,
2209 port_declaration_context.data_type,
2213 // Otherwise, the decorations for this identifier
2214 // indicate the type. Save the type for any right
2215 // context that may come later.
2216 port_declaration_context.port_type = use_port_type;
2218 $2 = new vector_type_t(IVL_VT_LOGIC, false, 0);
2221 port_declaration_context.data_type = $2;
2222 tmp = pform_make_task_ports(@3, use_port_type, $2, ilist);
2225 pform_set_reg_idx(name, $4);
2230 assert(tmp->size()==1);
2231 tmp->front().defe = $5;
2235 /* Rules to match error cases... */
2237 | port_direction_opt data_type_or_implicit IDENTIFIER error
2238 { yyerror(@3, "error: Error in task/function port item after port name %s.", $3);
2244 /* This rule matches the [ = <expression> ] part of the tf_port_item rules. */
2246 tf_port_item_expr_opt
2248 { if (! gn_system_verilog()) {
2249 yyerror(@1, "error: Task/function default arguments require "
2257 tf_port_list /* IEEE1800-2005: A.2.7 */
2258 : { port_declaration_context.port_type = gn_system_verilog() ? NetNet::PINPUT : NetNet::PIMPLICIT;
2259 port_declaration_context.data_type = 0;
2266 : tf_port_item_list ',' tf_port_item
2267 { vector<pform_tf_port_t>*tmp;
2269 size_t s1 = $1->size();
2271 tmp->resize(tmp->size()+$3->size());
2272 for (size_t idx = 0 ; idx < $3->size() ; idx += 1)
2273 tmp->at(s1+idx) = $3->at(idx);
2286 /* Rules to handle some errors in tf_port_list items. */
2288 | error ',' tf_port_item
2289 { yyerror(@2, "error: Syntax error in task/function port declaration.");
2292 | tf_port_item_list ','
2293 { yyerror(@2, "error: NULL port declarations are not allowed.");
2296 | tf_port_item_list ';'
2297 { yyerror(@2, "error: ';' is an invalid port declaration separator.");
2302 timeunits_declaration /* IEEE1800-2005: A.1.2 */
2303 : K_timeunit TIME_LITERAL ';'
2304 { pform_set_timeunit($2, allow_timeunit_decl); }
2305 | K_timeunit TIME_LITERAL '/' TIME_LITERAL ';'
2306 { bool initial_decl = allow_timeunit_decl && allow_timeprec_decl;
2307 pform_set_timeunit($2, initial_decl);
2308 pform_set_timeprec($4, initial_decl);
2310 | K_timeprecision TIME_LITERAL ';'
2311 { pform_set_timeprec($2, allow_timeprec_decl); }
2314 /* Allow zero, one, or two declarations. The second declaration might
2315 be a repeat declaration, but the pform functions take care of that. */
2316 timeunits_declaration_opt
2317 : /* empty */ %prec no_timeunits_declaration
2318 | timeunits_declaration %prec one_timeunits_declaration
2319 | timeunits_declaration timeunits_declaration
2322 value_range /* IEEE1800-2005: A.8.3 */
2325 | '[' expression ':' expression ']'
2329 variable_dimension /* IEEE1800-2005: A.2.5 */
2330 : '[' expression ':' expression ']'
2331 { list<pform_range_t> *tmp = new list<pform_range_t>;
2332 pform_range_t index ($2,$4);
2333 tmp->push_back(index);
2336 | '[' expression ']'
2337 { // SystemVerilog canonical range
2338 if (!gn_system_verilog()) {
2340 cerr << @2 << ": warning: Use of SystemVerilog [size] dimension. "
2341 << "Use at least -g2005-sv to remove this warning." << endl;
2343 list<pform_range_t> *tmp = new list<pform_range_t>;
2344 pform_range_t index;
2345 index.first = new PENumber(new verinum((uint64_t)0, integer_width));
2346 index.second = new PEBinary('-', $2, new PENumber(new verinum((uint64_t)1, integer_width)));
2347 tmp->push_back(index);
2351 { list<pform_range_t> *tmp = new list<pform_range_t>;
2352 pform_range_t index (0,0);
2353 tmp->push_back(index);
2357 { // SystemVerilog queue
2358 list<pform_range_t> *tmp = new list<pform_range_t>;
2359 pform_range_t index (new PENull,0);
2360 if (!gn_system_verilog()) {
2361 yyerror("error: Queue declarations require SystemVerilog.");
2363 tmp->push_back(index);
2370 { if (!gn_system_verilog()) {
2371 yyerror(@1, "error: overriding the default variable lifetime "
2372 "requires SystemVerilog.");
2373 } else if ($1 != pform_peek_scope()->default_lifetime) {
2374 yyerror(@1, "sorry: overriding the default variable lifetime "
2375 "is not yet supported.");
2381 /* Verilog-2001 supports attribute lists, which can be attached to a
2382 variety of different objects. The syntax inside the (* *) is a
2383 comma separated list of names or names with assigned values. */
2385 : attribute_instance_list
2391 attribute_instance_list
2392 : K_PSTAR K_STARP { $$ = 0; }
2393 | K_PSTAR attribute_list K_STARP { $$ = $2; }
2394 | attribute_instance_list K_PSTAR K_STARP { $$ = $1; }
2395 | attribute_instance_list K_PSTAR attribute_list K_STARP
2396 { list<named_pexpr_t>*tmp = $1;
2398 tmp->splice(tmp->end(), *$3);
2406 : attribute_list ',' attribute
2407 { list<named_pexpr_t>*tmp = $1;
2408 tmp->push_back(*$3);
2413 { list<named_pexpr_t>*tmp = new list<named_pexpr_t>;
2414 tmp->push_back(*$1);
2423 { named_pexpr_t*tmp = new named_pexpr_t;
2424 tmp->name = lex_strings.make($1);
2429 | IDENTIFIER '=' expression
2431 named_pexpr_t*tmp2 = new named_pexpr_t;
2432 tmp2->name = lex_strings.make($1);
2440 /* The block_item_decl is used in function definitions, task
2441 definitions, module definitions and named blocks. Wherever a new
2442 scope is entered, the source may declare new registers and
2443 integers. This rule matches those declarations. The containing
2444 rule has presumably set up the scope. */
2448 /* variable declarations. Note that data_type can be 0 if we are
2449 recovering from an error. */
2451 : data_type register_variable_list ';'
2452 { if ($1) pform_set_data_type(@1, $1, $2, NetNet::REG, attributes_in_context);
2455 | variable_lifetime data_type register_variable_list ';'
2456 { if ($2) pform_set_data_type(@2, $2, $3, NetNet::REG, attributes_in_context);
2457 var_lifetime = LexicalScope::INHERITED;
2460 | K_reg data_type register_variable_list ';'
2461 { if ($2) pform_set_data_type(@2, $2, $3, NetNet::REG, attributes_in_context);
2464 | variable_lifetime K_reg data_type register_variable_list ';'
2465 { if ($3) pform_set_data_type(@3, $3, $4, NetNet::REG, attributes_in_context);
2466 var_lifetime = LexicalScope::INHERITED;
2469 | K_event event_variable_list ';'
2470 { if ($2) pform_make_events($2, @1.text, @1.first_line);
2473 | K_parameter param_type parameter_assign_list ';'
2474 | K_localparam param_type localparam_assign_list ';'
2476 /* Blocks can have type declarations. */
2480 /* Recover from errors that happen within variable lists. Use the
2481 trailing semi-colon to resync the parser. */
2483 | K_integer error ';'
2484 { yyerror(@1, "error: syntax error in integer variable list.");
2489 { yyerror(@1, "error: syntax error in time variable list.");
2493 | K_parameter error ';'
2494 { yyerror(@1, "error: syntax error in parameter list.");
2497 | K_localparam error ';'
2498 { yyerror(@1, "error: syntax error localparam list.");
2505 | block_item_decls block_item_decl
2508 block_item_decls_opt
2509 : block_item_decls { $$ = true; }
2513 /* Type declarations are parsed here. The rule actions call pform
2514 functions that add the declaration to the current lexical scope. */
2516 : K_typedef data_type IDENTIFIER dimensions_opt ';'
2517 { perm_string name = lex_strings.make($3);
2518 pform_set_typedef(name, $2, $4);
2522 /* If the IDENTIFIER already is a typedef, it is possible for this
2523 code to override the definition, but only if the typedef is
2524 inherited from a different scope. */
2525 | K_typedef data_type TYPE_IDENTIFIER ';'
2526 { perm_string name = lex_strings.make($3.text);
2527 if (pform_test_type_identifier_local(name)) {
2528 yyerror(@3, "error: Typedef identifier \"%s\" is already a type name.", $3.text);
2531 pform_set_typedef(name, $2, NULL);
2536 /* These are forward declarations... */
2538 | K_typedef K_class IDENTIFIER ';'
2539 { // Create a synthetic typedef for the class name so that the
2540 // lexor detects the name as a type.
2541 perm_string name = lex_strings.make($3);
2542 class_type_t*tmp = new class_type_t(name);
2544 pform_set_typedef(name, tmp, NULL);
2547 | K_typedef K_enum IDENTIFIER ';'
2548 { yyerror(@1, "sorry: Enum forward declarations not supported yet."); }
2549 | K_typedef K_struct IDENTIFIER ';'
2550 { yyerror(@1, "sorry: Struct forward declarations not supported yet."); }
2551 | K_typedef K_union IDENTIFIER ';'
2552 { yyerror(@1, "sorry: Union forward declarations not supported yet."); }
2553 | K_typedef IDENTIFIER ';'
2554 { // Create a synthetic typedef for the class name so that the
2555 // lexor detects the name as a type.
2556 perm_string name = lex_strings.make($2);
2557 class_type_t*tmp = new class_type_t(name);
2559 pform_set_typedef(name, tmp, NULL);
2563 | K_typedef error ';'
2564 { yyerror(@2, "error: Syntax error in typedef clause.");
2570 /* The structure for an enumeration data type is the keyword "enum",
2571 followed by the enumeration values in curly braces. Also allow
2572 for an optional base type. The default base type is "int", but it
2573 can be any of the integral or vector types. */
2576 : K_enum '{' enum_name_list '}'
2577 { enum_type_t*enum_type = new enum_type_t;
2578 FILE_NAME(enum_type, @1);
2579 enum_type->names .reset($3);
2580 enum_type->base_type = IVL_VT_BOOL;
2581 enum_type->signed_flag = true;
2582 enum_type->integer_flag = false;
2583 enum_type->range.reset(make_range_from_width(32));
2586 | K_enum atom2_type signed_unsigned_opt '{' enum_name_list '}'
2587 { enum_type_t*enum_type = new enum_type_t;
2588 FILE_NAME(enum_type, @1);
2589 enum_type->names .reset($5);
2590 enum_type->base_type = IVL_VT_BOOL;
2591 enum_type->signed_flag = $3;
2592 enum_type->integer_flag = false;
2593 enum_type->range.reset(make_range_from_width($2));
2596 | K_enum K_integer signed_unsigned_opt '{' enum_name_list '}'
2597 { enum_type_t*enum_type = new enum_type_t;
2598 FILE_NAME(enum_type, @1);
2599 enum_type->names .reset($5);
2600 enum_type->base_type = IVL_VT_LOGIC;
2601 enum_type->signed_flag = $3;
2602 enum_type->integer_flag = true;
2603 enum_type->range.reset(make_range_from_width(integer_width));
2606 | K_enum K_logic unsigned_signed_opt dimensions_opt '{' enum_name_list '}'
2607 { enum_type_t*enum_type = new enum_type_t;
2608 FILE_NAME(enum_type, @1);
2609 enum_type->names .reset($6);
2610 enum_type->base_type = IVL_VT_LOGIC;
2611 enum_type->signed_flag = $3;
2612 enum_type->integer_flag = false;
2613 enum_type->range.reset($4 ? $4 : make_range_from_width(1));
2616 | K_enum K_reg unsigned_signed_opt dimensions_opt '{' enum_name_list '}'
2617 { enum_type_t*enum_type = new enum_type_t;
2618 FILE_NAME(enum_type, @1);
2619 enum_type->names .reset($6);
2620 enum_type->base_type = IVL_VT_LOGIC;
2621 enum_type->signed_flag = $3;
2622 enum_type->integer_flag = false;
2623 enum_type->range.reset($4 ? $4 : make_range_from_width(1));
2626 | K_enum K_bit unsigned_signed_opt dimensions_opt '{' enum_name_list '}'
2627 { enum_type_t*enum_type = new enum_type_t;
2628 FILE_NAME(enum_type, @1);
2629 enum_type->names .reset($6);
2630 enum_type->base_type = IVL_VT_BOOL;
2631 enum_type->signed_flag = $3;
2632 enum_type->integer_flag = false;
2633 enum_type->range.reset($4 ? $4 : make_range_from_width(1));
2642 | enum_name_list ',' enum_name
2643 { list<named_pexpr_t>*lst = $1;
2644 lst->splice(lst->end(), *$3);
2655 { verinum tmp = -(*($2));
2663 { perm_string name = lex_strings.make($1);
2665 $$ = make_named_number(name);
2667 | IDENTIFIER '[' pos_neg_number ']'
2668 { perm_string name = lex_strings.make($1);
2669 long count = check_enum_seq_value(@1, $3, false);
2671 $$ = make_named_numbers(name, 0, count-1);
2674 | IDENTIFIER '[' pos_neg_number ':' pos_neg_number ']'
2675 { perm_string name = lex_strings.make($1);
2676 $$ = make_named_numbers(name, check_enum_seq_value(@1, $3, true),
2677 check_enum_seq_value(@1, $5, true));
2682 | IDENTIFIER '=' expression
2683 { perm_string name = lex_strings.make($1);
2685 $$ = make_named_number(name, $3);
2687 | IDENTIFIER '[' pos_neg_number ']' '=' expression
2688 { perm_string name = lex_strings.make($1);
2689 long count = check_enum_seq_value(@1, $3, false);
2690 $$ = make_named_numbers(name, 0, count-1, $6);
2694 | IDENTIFIER '[' pos_neg_number ':' pos_neg_number ']' '=' expression
2695 { perm_string name = lex_strings.make($1);
2696 $$ = make_named_numbers(name, check_enum_seq_value(@1, $3, true),
2697 check_enum_seq_value(@1, $5, true), $8);
2705 : K_struct K_packed_opt '{' struct_union_member_list '}'
2706 { struct_type_t*tmp = new struct_type_t;
2708 tmp->packed_flag = $2;
2709 tmp->union_flag = false;
2710 tmp->members .reset($4);
2713 | K_union K_packed_opt '{' struct_union_member_list '}'
2714 { struct_type_t*tmp = new struct_type_t;
2716 tmp->packed_flag = $2;
2717 tmp->union_flag = true;
2718 tmp->members .reset($4);
2721 | K_struct K_packed_opt '{' error '}'
2722 { yyerror(@3, "error: Errors in struct member list.");
2724 struct_type_t*tmp = new struct_type_t;
2726 tmp->packed_flag = $2;
2727 tmp->union_flag = false;
2730 | K_union K_packed_opt '{' error '}'
2731 { yyerror(@3, "error: Errors in union member list.");
2733 struct_type_t*tmp = new struct_type_t;
2735 tmp->packed_flag = $2;
2736 tmp->union_flag = true;
2741 /* This is an implementation of the rule snippet:
2742 struct_union_member { struct_union_member }
2743 that is used in the rule matching struct and union types
2744 in IEEE 1800-2012 A.2.2.1. */
2745 struct_union_member_list
2746 : struct_union_member_list struct_union_member
2747 { list<struct_member_t*>*tmp = $1;
2751 | struct_union_member
2752 { list<struct_member_t*>*tmp = new list<struct_member_t*>;
2758 struct_union_member /* IEEE 1800-2012 A.2.2.1 */
2759 : attribute_list_opt data_type list_of_variable_decl_assignments ';'
2760 { struct_member_t*tmp = new struct_member_t;
2762 tmp->type .reset($2);
2763 tmp->names .reset($3);
2767 { yyerror(@2, "Error in struct/union member.");
2774 : expression_list_proper ':' statement_or_null
2775 { PCase::Item*tmp = new PCase::Item;
2781 | K_default ':' statement_or_null
2782 { PCase::Item*tmp = new PCase::Item;
2786 | K_default statement_or_null
2787 { PCase::Item*tmp = new PCase::Item;
2791 | error ':' statement_or_null
2792 { yyerror(@2, "error: Incomprehensible case expression.");
2798 : case_items case_item
2799 { svector<PCase::Item*>*tmp;
2800 tmp = new svector<PCase::Item*>(*$1, $2);
2805 { svector<PCase::Item*>*tmp = new svector<PCase::Item*>(1);
2823 : hierarchy_identifier '=' expression
2824 { pform_set_defparam(*$1, $3);
2829 defparam_assign_list
2831 | dimensions defparam_assign
2832 { yyerror(@1, "error: defparam may not include a range.");
2835 | defparam_assign_list ',' defparam_assign
2839 : '#' delay_value_simple
2840 { list<PExpr*>*tmp = new list<PExpr*>;
2844 | '#' '(' delay_value ')'
2845 { list<PExpr*>*tmp = new list<PExpr*>;
2852 : '#' delay_value_simple
2853 { list<PExpr*>*tmp = new list<PExpr*>;
2857 | '#' '(' delay_value ')'
2858 { list<PExpr*>*tmp = new list<PExpr*>;
2862 | '#' '(' delay_value ',' delay_value ')'
2863 { list<PExpr*>*tmp = new list<PExpr*>;
2868 | '#' '(' delay_value ',' delay_value ',' delay_value ')'
2869 { list<PExpr*>*tmp = new list<PExpr*>;
2878 : delay3 { $$ = $1; }
2884 { list<PExpr*>*tmp = new list<PExpr*>;
2888 | delay_value_list ',' delay_value
2889 { list<PExpr*>*tmp = $1;
2900 | expression ':' expression ':' expression
2901 { $$ = pform_select_mtm_expr($1, $3, $5); }
2909 yyerror(@1, "internal error: delay.");
2912 $$ = new PENumber(tmp);
2918 { verireal*tmp = $1;
2920 yyerror(@1, "internal error: delay.");
2923 $$ = new PEFNumber(tmp);
2928 { PEIdent*tmp = new PEIdent(lex_strings.make($1));
2938 if ($1 == 0 || !get_time_unit($1, unit))
2939 yyerror(@1, "internal error: delay.");
2941 double p = pow(10.0,
2942 (double)(unit - pform_get_timeunit()));
2943 double time = atof($1) * p;
2945 verireal *v = new verireal(time);
2946 $$ = new PEFNumber(v);
2952 /* The discipline and nature declarations used to take no ';' after
2953 the identifier. The 2.3 LRM adds the ';', but since there are
2954 programs written to the 2.1 and 2.2 standard that don't, we
2955 choose to make the ';' optional in this context. */
2956 optional_semicolon : ';' | ;
2958 discipline_declaration
2959 : K_discipline IDENTIFIER optional_semicolon
2960 { pform_start_discipline($2); }
2961 discipline_items K_enddiscipline
2962 { pform_end_discipline(@1); delete[] $2; }
2966 : discipline_items discipline_item
2971 : K_domain K_discrete ';'
2972 { pform_discipline_domain(@1, IVL_DIS_DISCRETE); }
2973 | K_domain K_continuous ';'
2974 { pform_discipline_domain(@1, IVL_DIS_CONTINUOUS); }
2975 | K_potential IDENTIFIER ';'
2976 { pform_discipline_potential(@1, $2); delete[] $2; }
2977 | K_flow IDENTIFIER ';'
2978 { pform_discipline_flow(@1, $2); delete[] $2; }
2982 : K_nature IDENTIFIER optional_semicolon
2983 { pform_start_nature($2); }
2986 { pform_end_nature(@1); delete[] $2; }
2990 : nature_items nature_item
2995 : K_units '=' STRING ';'
2997 | K_abstol '=' expression ';'
2998 | K_access '=' IDENTIFIER ';'
2999 { pform_nature_access(@1, $3); delete[] $3; }
3000 | K_idt_nature '=' IDENTIFIER ';'
3002 | K_ddt_nature '=' IDENTIFIER ';'
3007 : K_config IDENTIFIER ';'
3008 K_design lib_cell_identifiers ';'
3009 list_of_config_rule_statements
3011 { cerr << @1 << ": sorry: config declarations are not supported and "
3012 "will be skipped." << endl;
3017 lib_cell_identifiers
3018 : /* The BNF implies this can be blank, but I'm not sure exactly what
3020 | lib_cell_identifiers lib_cell_id
3023 list_of_config_rule_statements
3024 : /* config rules are optional. */
3025 | list_of_config_rule_statements config_rule_statement
3028 config_rule_statement
3029 : K_default K_liblist list_of_libraries ';'
3030 | K_instance hierarchy_identifier K_liblist list_of_libraries ';'
3032 | K_instance hierarchy_identifier K_use lib_cell_id opt_config ';'
3034 | K_cell lib_cell_id K_liblist list_of_libraries ';'
3035 | K_cell lib_cell_id K_use lib_cell_id opt_config ';'
3039 : /* The use clause takes an optional :config. */
3046 | IDENTIFIER '.' IDENTIFIER
3047 { delete[] $1; delete[] $3; }
3051 : /* A NULL library means use the parents cell library. */
3052 | list_of_libraries IDENTIFIER
3057 : '(' dr_strength0 ',' dr_strength1 ')'
3058 { $$.str0 = $2.str0;
3061 | '(' dr_strength1 ',' dr_strength0 ')'
3062 { $$.str0 = $4.str0;
3065 | '(' dr_strength0 ',' K_highz1 ')'
3066 { $$.str0 = $2.str0;
3067 $$.str1 = IVL_DR_HiZ;
3069 | '(' dr_strength1 ',' K_highz0 ')'
3070 { $$.str0 = IVL_DR_HiZ;
3073 | '(' K_highz1 ',' dr_strength0 ')'
3074 { $$.str0 = $4.str0;
3075 $$.str1 = IVL_DR_HiZ;
3077 | '(' K_highz0 ',' dr_strength1 ')'
3078 { $$.str0 = IVL_DR_HiZ;
3084 : drive_strength { $$ = $1; }
3085 | { $$.str0 = IVL_DR_STRONG; $$.str1 = IVL_DR_STRONG; }
3089 : K_supply0 { $$.str0 = IVL_DR_SUPPLY; }
3090 | K_strong0 { $$.str0 = IVL_DR_STRONG; }
3091 | K_pull0 { $$.str0 = IVL_DR_PULL; }
3092 | K_weak0 { $$.str0 = IVL_DR_WEAK; }
3096 : K_supply1 { $$.str1 = IVL_DR_SUPPLY; }
3097 | K_strong1 { $$.str1 = IVL_DR_STRONG; }
3098 | K_pull1 { $$.str1 = IVL_DR_PULL; }
3099 | K_weak1 { $$.str1 = IVL_DR_WEAK; }
3102 clocking_event_opt /* */
3107 event_control /* A.K.A. clocking_event */
3108 : '@' hierarchy_identifier
3109 { PEIdent*tmpi = new PEIdent(*$2);
3110 PEEvent*tmpe = new PEEvent(PEEvent::ANYEDGE, tmpi);
3111 PEventStatement*tmps = new PEventStatement(tmpe);
3112 FILE_NAME(tmps, @1);
3116 | '@' '(' event_expression_list ')'
3117 { PEventStatement*tmp = new PEventStatement(*$3);
3123 { yyerror(@1, "error: Malformed event control expression.");
3128 event_expression_list
3131 | event_expression_list K_or event_expression
3132 { svector<PEEvent*>*tmp = new svector<PEEvent*>(*$1, *$3);
3137 | event_expression_list ',' event_expression
3138 { svector<PEEvent*>*tmp = new svector<PEEvent*>(*$1, *$3);
3146 : K_posedge expression
3147 { PEEvent*tmp = new PEEvent(PEEvent::POSEDGE, $2);
3149 svector<PEEvent*>*tl = new svector<PEEvent*>(1);
3153 | K_negedge expression
3154 { PEEvent*tmp = new PEEvent(PEEvent::NEGEDGE, $2);
3156 svector<PEEvent*>*tl = new svector<PEEvent*>(1);
3161 { PEEvent*tmp = new PEEvent(PEEvent::ANYEDGE, $1);
3163 svector<PEEvent*>*tl = new svector<PEEvent*>(1);
3169 /* A branch probe expression applies a probe function (potential or
3170 flow) to a branch. The branch may be implicit as a pair of nets
3171 or explicit as a named branch. Elaboration will check that the
3172 function name really is a nature attribute identifier. */
3173 branch_probe_expression
3174 : IDENTIFIER '(' IDENTIFIER ',' IDENTIFIER ')'
3175 { $$ = pform_make_branch_probe_expression(@1, $1, $3, $5); }
3176 | IDENTIFIER '(' IDENTIFIER ')'
3177 { $$ = pform_make_branch_probe_expression(@1, $1, $3); }
3181 : expr_primary_or_typename
3183 | inc_or_dec_expression
3187 | '+' attribute_list_opt expr_primary %prec UNARY_PREC
3189 | '-' attribute_list_opt expr_primary %prec UNARY_PREC
3190 { PEUnary*tmp = new PEUnary('-', $3);
3194 | '~' attribute_list_opt expr_primary %prec UNARY_PREC
3195 { PEUnary*tmp = new PEUnary('~', $3);
3199 | '&' attribute_list_opt expr_primary %prec UNARY_PREC
3200 { PEUnary*tmp = new PEUnary('&', $3);
3204 | '!' attribute_list_opt expr_primary %prec UNARY_PREC
3205 { PEUnary*tmp = new PEUnary('!', $3);
3209 | '|' attribute_list_opt expr_primary %prec UNARY_PREC
3210 { PEUnary*tmp = new PEUnary('|', $3);
3214 | '^' attribute_list_opt expr_primary %prec UNARY_PREC
3215 { PEUnary*tmp = new PEUnary('^', $3);
3219 | '~' '&' attribute_list_opt expr_primary %prec UNARY_PREC
3220 { yyerror(@1, "error: '~' '&' is not a valid expression. "
3221 "Please use operator '~&' instead.");
3224 | '~' '|' attribute_list_opt expr_primary %prec UNARY_PREC
3225 { yyerror(@1, "error: '~' '|' is not a valid expression. "
3226 "Please use operator '~|' instead.");
3229 | '~' '^' attribute_list_opt expr_primary %prec UNARY_PREC
3230 { yyerror(@1, "error: '~' '^' is not a valid expression. "
3231 "Please use operator '~^' instead.");
3234 | K_NAND attribute_list_opt expr_primary %prec UNARY_PREC
3235 { PEUnary*tmp = new PEUnary('A', $3);
3239 | K_NOR attribute_list_opt expr_primary %prec UNARY_PREC
3240 { PEUnary*tmp = new PEUnary('N', $3);
3244 | K_NXOR attribute_list_opt expr_primary %prec UNARY_PREC
3245 { PEUnary*tmp = new PEUnary('X', $3);
3249 | '!' error %prec UNARY_PREC
3250 { yyerror(@1, "error: Operand of unary ! "
3251 "is not a primary expression.");
3254 | '^' error %prec UNARY_PREC
3255 { yyerror(@1, "error: Operand of reduction ^ "
3256 "is not a primary expression.");
3259 | expression '^' attribute_list_opt expression
3260 { PEBinary*tmp = new PEBinary('^', $1, $4);
3264 | expression K_POW attribute_list_opt expression
3265 { PEBinary*tmp = new PEBPower('p', $1, $4);
3269 | expression '*' attribute_list_opt expression
3270 { PEBinary*tmp = new PEBinary('*', $1, $4);
3274 | expression '/' attribute_list_opt expression
3275 { PEBinary*tmp = new PEBinary('/', $1, $4);
3279 | expression '%' attribute_list_opt expression
3280 { PEBinary*tmp = new PEBinary('%', $1, $4);
3284 | expression '+' attribute_list_opt expression
3285 { PEBinary*tmp = new PEBinary('+', $1, $4);
3289 | expression '-' attribute_list_opt expression
3290 { PEBinary*tmp = new PEBinary('-', $1, $4);
3294 | expression '&' attribute_list_opt expression
3295 { PEBinary*tmp = new PEBinary('&', $1, $4);
3299 | expression '|' attribute_list_opt expression
3300 { PEBinary*tmp = new PEBinary('|', $1, $4);
3304 | expression K_NAND attribute_list_opt expression
3305 { PEBinary*tmp = new PEBinary('A', $1, $4);
3309 | expression K_NOR attribute_list_opt expression
3310 { PEBinary*tmp = new PEBinary('O', $1, $4);
3314 | expression K_NXOR attribute_list_opt expression
3315 { PEBinary*tmp = new PEBinary('X', $1, $4);
3319 | expression '<' attribute_list_opt expression
3320 { PEBinary*tmp = new PEBComp('<', $1, $4);
3324 | expression '>' attribute_list_opt expression
3325 { PEBinary*tmp = new PEBComp('>', $1, $4);
3329 | expression K_LS attribute_list_opt expression
3330 { PEBinary*tmp = new PEBShift('l', $1, $4);
3334 | expression K_RS attribute_list_opt expression
3335 { PEBinary*tmp = new PEBShift('r', $1, $4);
3339 | expression K_RSS attribute_list_opt expression
3340 { PEBinary*tmp = new PEBShift('R', $1, $4);
3344 | expression K_EQ attribute_list_opt expression
3345 { PEBinary*tmp = new PEBComp('e', $1, $4);
3349 | expression K_CEQ attribute_list_opt expression
3350 { PEBinary*tmp = new PEBComp('E', $1, $4);
3354 | expression K_WEQ attribute_list_opt expression
3355 { PEBinary*tmp = new PEBComp('w', $1, $4);
3359 | expression K_LE attribute_list_opt expression
3360 { PEBinary*tmp = new PEBComp('L', $1, $4);
3364 | expression K_GE attribute_list_opt expression
3365 { PEBinary*tmp = new PEBComp('G', $1, $4);
3369 | expression K_NE attribute_list_opt expression
3370 { PEBinary*tmp = new PEBComp('n', $1, $4);
3374 | expression K_CNE attribute_list_opt expression
3375 { PEBinary*tmp = new PEBComp('N', $1, $4);
3379 | expression K_WNE attribute_list_opt expression
3380 { PEBinary*tmp = new PEBComp('W', $1, $4);
3384 | expression K_LOR attribute_list_opt expression
3385 { PEBinary*tmp = new PEBLogic('o', $1, $4);
3389 | expression K_LAND attribute_list_opt expression
3390 { PEBinary*tmp = new PEBLogic('a', $1, $4);
3394 | expression '?' attribute_list_opt expression ':' expression
3395 { PETernary*tmp = new PETernary($1, $4, $6);
3404 | expression ':' expression ':' expression
3405 { switch (min_typ_max_flag) {
3422 if (min_typ_max_warn > 0) {
3423 cerr << $$->get_fileline() << ": warning: choosing ";
3424 switch (min_typ_max_flag) {
3435 cerr << " expression." << endl;
3436 min_typ_max_warn -= 1;
3442 /* Many contexts take a comma separated list of expressions. Null
3443 expressions can happen anywhere in the list, so there are two
3444 extra rules in expression_list_with_nuls for parsing and
3445 installing those nulls.
3447 The expression_list_proper rules do not allow null items in the
3448 expression list, so can be used where nul expressions are not allowed. */
3450 expression_list_with_nuls
3451 : expression_list_with_nuls ',' expression
3452 { list<PExpr*>*tmp = $1;
3457 { list<PExpr*>*tmp = new list<PExpr*>;
3462 { list<PExpr*>*tmp = new list<PExpr*>;
3466 | expression_list_with_nuls ','
3467 { list<PExpr*>*tmp = $1;
3473 expression_list_proper
3474 : expression_list_proper ',' expression
3475 { list<PExpr*>*tmp = $1;
3480 { list<PExpr*>*tmp = new list<PExpr*>;
3486 expr_primary_or_typename
3489 /* There are a few special cases (notably $bits argument) where the
3490 expression may be a type name. Let the elaborator sort this out. */
3492 { PETypename*tmp = new PETypename($1.type);
3503 PENumber*tmp = new PENumber($1);
3508 { PEFNumber*tmp = new PEFNumber($1);
3513 { PEString*tmp = new PEString($1);
3522 if ($1 == 0 || !get_time_unit($1, unit))
3523 yyerror(@1, "internal error: delay.");
3525 double p = pow(10.0, (double)(unit - pform_get_timeunit()));
3526 double time = atof($1) * p;
3528 verireal *v = new verireal(time);
3529 $$ = new PEFNumber(v);
3534 { perm_string tn = lex_strings.make($1);
3535 PECallFunction*tmp = new PECallFunction(tn);
3541 /* The hierarchy_identifier rule matches simple identifiers as well as
3542 indexed arrays and part selects */
3544 | hierarchy_identifier
3545 { PEIdent*tmp = pform_new_ident(*$1);
3551 | PACKAGE_IDENTIFIER K_SCOPE_RES hierarchy_identifier
3552 { $$ = pform_package_ident(@2, $1, $3);
3556 /* An identifier followed by an expression list in parentheses is a
3557 function call. If a system identifier, then a system function
3558 call. It can also be a call to a class method (function). */
3560 | hierarchy_identifier '(' expression_list_with_nuls ')'
3561 { list<PExpr*>*expr_list = $3;
3562 strip_tail_items(expr_list);
3563 PECallFunction*tmp = pform_make_call_function(@1, *$1, *expr_list);
3567 | implicit_class_handle '.' hierarchy_identifier '(' expression_list_with_nuls ')'
3568 { pform_name_t*t_name = $1;
3569 while (! $3->empty()) {
3570 t_name->push_back($3->front());
3573 list<PExpr*>*expr_list = $5;
3574 strip_tail_items(expr_list);
3575 PECallFunction*tmp = pform_make_call_function(@1, *t_name, *expr_list);
3580 | SYSTEM_IDENTIFIER '(' expression_list_proper ')'
3581 { perm_string tn = lex_strings.make($1);
3582 PECallFunction*tmp = new PECallFunction(tn, *$3);
3587 | PACKAGE_IDENTIFIER K_SCOPE_RES IDENTIFIER '(' expression_list_proper ')'
3588 { perm_string use_name = lex_strings.make($3);
3589 PECallFunction*tmp = new PECallFunction($1, use_name, *$5);
3594 | SYSTEM_IDENTIFIER '(' ')'
3595 { perm_string tn = lex_strings.make($1);
3596 const vector<PExpr*>empty;
3597 PECallFunction*tmp = new PECallFunction(tn, empty);
3601 if (!gn_system_verilog()) {
3602 yyerror(@1, "error: Empty function argument list requires SystemVerilog.");
3606 | implicit_class_handle
3607 { PEIdent*tmp = new PEIdent(*$1);
3613 | implicit_class_handle '.' hierarchy_identifier
3614 { pform_name_t*t_name = $1;
3615 while (! $3->empty()) {
3616 t_name->push_back($3->front());
3619 PEIdent*tmp = new PEIdent(*t_name);
3626 /* Many of the VAMS built-in functions are available as builtin
3627 functions with $system_function equivalents. */
3629 | K_acos '(' expression ')'
3630 { perm_string tn = perm_string::literal("$acos");
3631 PECallFunction*tmp = make_call_function(tn, $3);
3636 | K_acosh '(' expression ')'
3637 { perm_string tn = perm_string::literal("$acosh");
3638 PECallFunction*tmp = make_call_function(tn, $3);
3643 | K_asin '(' expression ')'
3644 { perm_string tn = perm_string::literal("$asin");
3645 PECallFunction*tmp = make_call_function(tn, $3);
3650 | K_asinh '(' expression ')'
3651 { perm_string tn = perm_string::literal("$asinh");
3652 PECallFunction*tmp = make_call_function(tn, $3);
3657 | K_atan '(' expression ')'
3658 { perm_string tn = perm_string::literal("$atan");
3659 PECallFunction*tmp = make_call_function(tn, $3);
3664 | K_atanh '(' expression ')'
3665 { perm_string tn = perm_string::literal("$atanh");
3666 PECallFunction*tmp = make_call_function(tn, $3);
3671 | K_atan2 '(' expression ',' expression ')'
3672 { perm_string tn = perm_string::literal("$atan2");
3673 PECallFunction*tmp = make_call_function(tn, $3, $5);
3678 | K_ceil '(' expression ')'
3679 { perm_string tn = perm_string::literal("$ceil");
3680 PECallFunction*tmp = make_call_function(tn, $3);
3685 | K_cos '(' expression ')'
3686 { perm_string tn = perm_string::literal("$cos");
3687 PECallFunction*tmp = make_call_function(tn, $3);
3692 | K_cosh '(' expression ')'
3693 { perm_string tn = perm_string::literal("$cosh");
3694 PECallFunction*tmp = make_call_function(tn, $3);
3699 | K_exp '(' expression ')'
3700 { perm_string tn = perm_string::literal("$exp");
3701 PECallFunction*tmp = make_call_function(tn, $3);
3706 | K_floor '(' expression ')'
3707 { perm_string tn = perm_string::literal("$floor");
3708 PECallFunction*tmp = make_call_function(tn, $3);
3713 | K_hypot '(' expression ',' expression ')'
3714 { perm_string tn = perm_string::literal("$hypot");
3715 PECallFunction*tmp = make_call_function(tn, $3, $5);
3720 | K_ln '(' expression ')'
3721 { perm_string tn = perm_string::literal("$ln");
3722 PECallFunction*tmp = make_call_function(tn, $3);
3727 | K_log '(' expression ')'
3728 { perm_string tn = perm_string::literal("$log10");
3729 PECallFunction*tmp = make_call_function(tn, $3);
3734 | K_pow '(' expression ',' expression ')'
3735 { perm_string tn = perm_string::literal("$pow");
3736 PECallFunction*tmp = make_call_function(tn, $3, $5);
3741 | K_sin '(' expression ')'
3742 { perm_string tn = perm_string::literal("$sin");
3743 PECallFunction*tmp = make_call_function(tn, $3);
3748 | K_sinh '(' expression ')'
3749 { perm_string tn = perm_string::literal("$sinh");
3750 PECallFunction*tmp = make_call_function(tn, $3);
3755 | K_sqrt '(' expression ')'
3756 { perm_string tn = perm_string::literal("$sqrt");
3757 PECallFunction*tmp = make_call_function(tn, $3);
3762 | K_tan '(' expression ')'
3763 { perm_string tn = perm_string::literal("$tan");
3764 PECallFunction*tmp = make_call_function(tn, $3);
3769 | K_tanh '(' expression ')'
3770 { perm_string tn = perm_string::literal("$tanh");
3771 PECallFunction*tmp = make_call_function(tn, $3);
3776 /* These mathematical functions are conveniently expressed as unary
3777 and binary expressions. They behave much like unary/binary
3778 operators, even though they are parsed as functions. */
3780 | K_abs '(' expression ')'
3781 { PEUnary*tmp = new PEUnary('m', $3);
3786 | K_max '(' expression ',' expression ')'
3787 { PEBinary*tmp = new PEBinary('M', $3, $5);
3792 | K_min '(' expression ',' expression ')'
3793 { PEBinary*tmp = new PEBinary('m', $3, $5);
3798 /* Parenthesized expressions are primaries. */
3800 | '(' expr_mintypmax ')'
3803 /* Various kinds of concatenation expressions. */
3805 | '{' expression_list_proper '}'
3806 { PEConcat*tmp = new PEConcat(*$2);
3811 | '{' expression '{' expression_list_proper '}' '}'
3813 PEConcat*tmp = new PEConcat(*$4, rep);
3818 | '{' expression '{' expression_list_proper '}' error '}'
3820 PEConcat*tmp = new PEConcat(*$4, rep);
3824 yyerror(@5, "error: Syntax error between internal '}' "
3825 "and closing '}' of repeat concatenation.");
3830 { // This is the empty queue syntax.
3831 if (gn_system_verilog()) {
3832 list<PExpr*> empty_list;
3833 PEConcat*tmp = new PEConcat(empty_list);
3837 yyerror(@1, "error: Concatenations are not allowed to be empty.");
3842 /* Cast expressions are primaries */
3844 | expr_primary "'" '(' expression ')'
3846 if (gn_system_verilog()) {
3847 PECastSize*tmp = new PECastSize($1, base);
3851 yyerror(@1, "error: Size cast requires SystemVerilog.");
3856 | simple_type_or_string "'" '(' expression ')'
3858 if (gn_system_verilog()) {
3859 PECastType*tmp = new PECastType($1, base);
3863 yyerror(@1, "error: Type cast requires SystemVerilog.");
3868 /* Aggregate literals are primaries. */
3870 | assignment_pattern
3873 /* SystemVerilog supports streaming concatenation */
3874 | streaming_concatenation
3878 { PENull*tmp = new PENull;
3884 /* A function_item_list borrows the task_port_item run to match
3885 declarations of ports. We check later to make sure there are no
3886 output or inout ports actually used.
3888 The function_item is the same as tf_item_declaration. */
3889 function_item_list_opt
3890 : function_item_list { $$ = $1; }
3897 | function_item_list function_item
3900 vector<pform_tf_port_t>*tmp = $1;
3901 size_t s1 = tmp->size();
3902 tmp->resize(s1 + $2->size());
3903 for (size_t idx = 0 ; idx < $2->size() ; idx += 1)
3904 tmp->at(s1+idx) = $2->at(idx);
3916 : tf_port_declaration
3922 /* A gate_instance is a module instantiation or a built in part
3923 type. In any case, the gate has a set of connections to ports. */
3925 : IDENTIFIER '(' expression_list_with_nuls ')'
3926 { lgate*tmp = new lgate;
3929 tmp->file = @1.text;
3930 tmp->lineno = @1.first_line;
3935 | IDENTIFIER dimensions '(' expression_list_with_nuls ')'
3936 { lgate*tmp = new lgate;
3937 list<pform_range_t>*rng = $2;
3940 tmp->range = rng->front();
3942 assert(rng->empty());
3943 tmp->file = @1.text;
3944 tmp->lineno = @1.first_line;
3950 | '(' expression_list_with_nuls ')'
3951 { lgate*tmp = new lgate;
3954 tmp->file = @1.text;
3955 tmp->lineno = @1.first_line;
3959 /* Degenerate modules can have no ports. */
3961 | IDENTIFIER dimensions
3962 { lgate*tmp = new lgate;
3963 list<pform_range_t>*rng = $2;
3966 tmp->parms_by_name = 0;
3967 tmp->range = rng->front();
3969 assert(rng->empty());
3970 tmp->file = @1.text;
3971 tmp->lineno = @1.first_line;
3977 /* Modules can also take ports by port-name expressions. */
3979 | IDENTIFIER '(' port_name_list ')'
3980 { lgate*tmp = new lgate;
3983 tmp->parms_by_name = $3;
3984 tmp->file = @1.text;
3985 tmp->lineno = @1.first_line;
3990 | IDENTIFIER dimensions '(' port_name_list ')'
3991 { lgate*tmp = new lgate;
3992 list<pform_range_t>*rng = $2;
3995 tmp->parms_by_name = $4;
3996 tmp->range = rng->front();
3998 assert(rng->empty());
3999 tmp->file = @1.text;
4000 tmp->lineno = @1.first_line;
4006 | IDENTIFIER '(' error ')'
4007 { lgate*tmp = new lgate;
4010 tmp->parms_by_name = 0;
4011 tmp->file = @1.text;
4012 tmp->lineno = @1.first_line;
4013 yyerror(@2, "error: Syntax error in instance port "
4019 | IDENTIFIER dimensions '(' error ')'
4020 { lgate*tmp = new lgate;
4023 tmp->parms_by_name = 0;
4024 tmp->file = @1.text;
4025 tmp->lineno = @1.first_line;
4026 yyerror(@3, "error: Syntax error in instance port "
4034 : gate_instance_list ',' gate_instance
4035 { svector<lgate>*tmp1 = $1;
4037 svector<lgate>*out = new svector<lgate> (*tmp1, *tmp2);
4043 { svector<lgate>*tmp = new svector<lgate>(1);
4051 : K_and { $$ = PGBuiltin::AND; }
4052 | K_nand { $$ = PGBuiltin::NAND; }
4053 | K_or { $$ = PGBuiltin::OR; }
4054 | K_nor { $$ = PGBuiltin::NOR; }
4055 | K_xor { $$ = PGBuiltin::XOR; }
4056 | K_xnor { $$ = PGBuiltin::XNOR; }
4057 | K_buf { $$ = PGBuiltin::BUF; }
4058 | K_bufif0 { $$ = PGBuiltin::BUFIF0; }
4059 | K_bufif1 { $$ = PGBuiltin::BUFIF1; }
4060 | K_not { $$ = PGBuiltin::NOT; }
4061 | K_notif0 { $$ = PGBuiltin::NOTIF0; }
4062 | K_notif1 { $$ = PGBuiltin::NOTIF1; }
4066 : K_nmos { $$ = PGBuiltin::NMOS; }
4067 | K_rnmos { $$ = PGBuiltin::RNMOS; }
4068 | K_pmos { $$ = PGBuiltin::PMOS; }
4069 | K_rpmos { $$ = PGBuiltin::RPMOS; }
4070 | K_cmos { $$ = PGBuiltin::CMOS; }
4071 | K_rcmos { $$ = PGBuiltin::RCMOS; }
4072 | K_tran { $$ = PGBuiltin::TRAN; }
4073 | K_rtran { $$ = PGBuiltin::RTRAN; }
4074 | K_tranif0 { $$ = PGBuiltin::TRANIF0; }
4075 | K_tranif1 { $$ = PGBuiltin::TRANIF1; }
4076 | K_rtranif0 { $$ = PGBuiltin::RTRANIF0; }
4077 | K_rtranif1 { $$ = PGBuiltin::RTRANIF1; }
4081 /* A general identifier is a hierarchical name, with the right most
4082 name the base of the identifier. This rule builds up a
4083 hierarchical name from the left to the right, forming a list of
4086 hierarchy_identifier
4088 { $$ = new pform_name_t;
4089 $$->push_back(name_component_t(lex_strings.make($1)));
4092 | hierarchy_identifier '.' IDENTIFIER
4093 { pform_name_t * tmp = $1;
4094 tmp->push_back(name_component_t(lex_strings.make($3)));
4098 | hierarchy_identifier '[' expression ']'
4099 { pform_name_t * tmp = $1;
4100 name_component_t&tail = tmp->back();
4101 index_component_t itmp;
4102 itmp.sel = index_component_t::SEL_BIT;
4104 tail.index.push_back(itmp);
4107 | hierarchy_identifier '[' '$' ']'
4108 { pform_name_t * tmp = $1;
4109 name_component_t&tail = tmp->back();
4110 if (! gn_system_verilog()) {
4111 yyerror(@3, "error: Last element expression ($) "
4112 "requires SystemVerilog. Try enabling SystemVerilog.");
4114 index_component_t itmp;
4115 itmp.sel = index_component_t::SEL_BIT_LAST;
4118 tail.index.push_back(itmp);
4121 | hierarchy_identifier '[' expression ':' expression ']'
4122 { pform_name_t * tmp = $1;
4123 name_component_t&tail = tmp->back();
4124 index_component_t itmp;
4125 itmp.sel = index_component_t::SEL_PART;
4128 tail.index.push_back(itmp);
4131 | hierarchy_identifier '[' expression K_PO_POS expression ']'
4132 { pform_name_t * tmp = $1;
4133 name_component_t&tail = tmp->back();
4134 index_component_t itmp;
4135 itmp.sel = index_component_t::SEL_IDX_UP;
4138 tail.index.push_back(itmp);
4141 | hierarchy_identifier '[' expression K_PO_NEG expression ']'
4142 { pform_name_t * tmp = $1;
4143 name_component_t&tail = tmp->back();
4144 index_component_t itmp;
4145 itmp.sel = index_component_t::SEL_IDX_DO;
4148 tail.index.push_back(itmp);
4153 /* This is a list of identifiers. The result is a list of strings,
4154 each one of the identifiers in the list. These are simple,
4155 non-hierarchical names separated by ',' characters. */
4158 { $$ = list_from_identifier($1); }
4159 | list_of_identifiers ',' IDENTIFIER
4160 { $$ = list_from_identifier($1, $3); }
4163 list_of_port_identifiers
4164 : IDENTIFIER dimensions_opt
4165 { $$ = make_port_list($1, $2, 0); }
4166 | list_of_port_identifiers ',' IDENTIFIER dimensions_opt
4167 { $$ = make_port_list($1, $3, $4, 0); }
4170 list_of_variable_port_identifiers
4171 : IDENTIFIER dimensions_opt
4172 { $$ = make_port_list($1, $2, 0); }
4173 | IDENTIFIER dimensions_opt '=' expression
4174 { $$ = make_port_list($1, $2, $4); }
4175 | list_of_variable_port_identifiers ',' IDENTIFIER dimensions_opt
4176 { $$ = make_port_list($1, $3, $4, 0); }
4177 | list_of_variable_port_identifiers ',' IDENTIFIER dimensions_opt '=' expression
4178 { $$ = make_port_list($1, $3, $4, $6); }
4182 /* The list_of_ports and list_of_port_declarations rules are the
4183 port list formats for module ports. The list_of_ports_opt rule is
4184 only used by the module start rule.
4186 The first, the list_of_ports, is the 1364-1995 format, a list of
4187 port names, including .name() syntax.
4189 The list_of_port_declarations the 1364-2001 format, an in-line
4190 declaration of the ports.
4192 In both cases, the list_of_ports and list_of_port_declarations
4193 returns an array of Module::port_t* items that include the name
4194 of the port internally and externally. The actual creation of the
4195 nets/variables is done in the declaration, whether internal to
4196 the port list or in amongst the module items. */
4200 { vector<Module::port_t*>*tmp
4201 = new vector<Module::port_t*>(1);
4205 | list_of_ports ',' port_opt
4206 { vector<Module::port_t*>*tmp = $1;
4212 list_of_port_declarations
4214 { vector<Module::port_t*>*tmp
4215 = new vector<Module::port_t*>(1);
4219 | list_of_port_declarations ',' port_declaration
4220 { vector<Module::port_t*>*tmp = $1;
4224 | list_of_port_declarations ',' IDENTIFIER
4225 { Module::port_t*ptmp;
4226 perm_string name = lex_strings.make($3);
4227 ptmp = pform_module_port_reference(name, @3.text,
4229 vector<Module::port_t*>*tmp = $1;
4230 tmp->push_back(ptmp);
4232 /* Get the port declaration details, the port type
4233 and what not, from context data stored by the
4234 last port_declaration rule. */
4235 pform_module_define_port(@3, name,
4236 port_declaration_context.port_type,
4237 port_declaration_context.port_net_type,
4238 port_declaration_context.data_type, 0);
4242 | list_of_port_declarations ','
4244 yyerror(@2, "error: NULL port declarations are not "
4247 | list_of_port_declarations ';'
4249 yyerror(@2, "error: ';' is an invalid port declaration "
4255 : attribute_list_opt K_input net_type_opt data_type_or_implicit IDENTIFIER dimensions_opt
4256 { Module::port_t*ptmp;
4257 perm_string name = lex_strings.make($5);
4258 data_type_t*use_type = $4;
4259 if ($6) use_type = new uarray_type_t(use_type, $6);
4260 ptmp = pform_module_port_reference(name, @2.text, @2.first_line);
4261 pform_module_define_port(@2, name, NetNet::PINPUT, $3, use_type, $1);
4262 port_declaration_context.port_type = NetNet::PINPUT;
4263 port_declaration_context.port_net_type = $3;
4264 port_declaration_context.data_type = $4;
4268 | attribute_list_opt
4269 K_input K_wreal IDENTIFIER
4270 { Module::port_t*ptmp;
4271 perm_string name = lex_strings.make($4);
4272 ptmp = pform_module_port_reference(name, @2.text,
4274 real_type_t*real_type = new real_type_t(real_type_t::REAL);
4275 FILE_NAME(real_type, @3);
4276 pform_module_define_port(@2, name, NetNet::PINPUT,
4277 NetNet::WIRE, real_type, $1);
4278 port_declaration_context.port_type = NetNet::PINPUT;
4279 port_declaration_context.port_net_type = NetNet::WIRE;
4280 port_declaration_context.data_type = real_type;
4284 | attribute_list_opt K_inout net_type_opt data_type_or_implicit IDENTIFIER dimensions_opt
4285 { Module::port_t*ptmp;
4286 perm_string name = lex_strings.make($5);
4287 ptmp = pform_module_port_reference(name, @2.text, @2.first_line);
4288 pform_module_define_port(@2, name, NetNet::PINOUT, $3, $4, $1);
4289 port_declaration_context.port_type = NetNet::PINOUT;
4290 port_declaration_context.port_net_type = $3;
4291 port_declaration_context.data_type = $4;
4294 yyerror(@6, "sorry: Inout ports with unpacked dimensions not supported.");
4299 | attribute_list_opt
4300 K_inout K_wreal IDENTIFIER
4301 { Module::port_t*ptmp;
4302 perm_string name = lex_strings.make($4);
4303 ptmp = pform_module_port_reference(name, @2.text,
4305 real_type_t*real_type = new real_type_t(real_type_t::REAL);
4306 FILE_NAME(real_type, @3);
4307 pform_module_define_port(@2, name, NetNet::PINOUT,
4308 NetNet::WIRE, real_type, $1);
4309 port_declaration_context.port_type = NetNet::PINOUT;
4310 port_declaration_context.port_net_type = NetNet::WIRE;
4311 port_declaration_context.data_type = real_type;
4315 | attribute_list_opt K_output net_type_opt data_type_or_implicit IDENTIFIER dimensions_opt
4316 { Module::port_t*ptmp;
4317 perm_string name = lex_strings.make($5);
4318 data_type_t*use_dtype = $4;
4319 if ($6) use_dtype = new uarray_type_t(use_dtype, $6);
4320 NetNet::Type use_type = $3;
4321 if (use_type == NetNet::IMPLICIT) {
4322 if (vector_type_t*dtype = dynamic_cast<vector_type_t*> ($4)) {
4323 if (dtype->reg_flag)
4324 use_type = NetNet::REG;
4325 else if (dtype->implicit_flag)
4326 use_type = NetNet::IMPLICIT;
4328 use_type = NetNet::IMPLICIT_REG;
4330 // The SystemVerilog types that can show up as
4331 // output ports are implicitly (on the inside)
4332 // variables because "reg" is not valid syntax
4334 } else if (dynamic_cast<atom2_type_t*> ($4)) {
4335 use_type = NetNet::IMPLICIT_REG;
4336 } else if (dynamic_cast<struct_type_t*> ($4)) {
4337 use_type = NetNet::IMPLICIT_REG;
4338 } else if (enum_type_t*etype = dynamic_cast<enum_type_t*> ($4)) {
4339 if(etype->base_type == IVL_VT_LOGIC)
4340 use_type = NetNet::IMPLICIT_REG;
4343 ptmp = pform_module_port_reference(name, @2.text, @2.first_line);
4344 pform_module_define_port(@2, name, NetNet::POUTPUT, use_type, use_dtype, $1);
4345 port_declaration_context.port_type = NetNet::POUTPUT;
4346 port_declaration_context.port_net_type = use_type;
4347 port_declaration_context.data_type = $4;
4351 | attribute_list_opt
4352 K_output K_wreal IDENTIFIER
4353 { Module::port_t*ptmp;
4354 perm_string name = lex_strings.make($4);
4355 ptmp = pform_module_port_reference(name, @2.text,
4357 real_type_t*real_type = new real_type_t(real_type_t::REAL);
4358 FILE_NAME(real_type, @3);
4359 pform_module_define_port(@2, name, NetNet::POUTPUT,
4360 NetNet::WIRE, real_type, $1);
4361 port_declaration_context.port_type = NetNet::POUTPUT;
4362 port_declaration_context.port_net_type = NetNet::WIRE;
4363 port_declaration_context.data_type = real_type;
4367 | attribute_list_opt K_output net_type_opt data_type_or_implicit IDENTIFIER '=' expression
4368 { Module::port_t*ptmp;
4369 perm_string name = lex_strings.make($5);
4370 NetNet::Type use_type = $3;
4371 if (use_type == NetNet::IMPLICIT) {
4372 if (vector_type_t*dtype = dynamic_cast<vector_type_t*> ($4)) {
4373 if (dtype->reg_flag)
4374 use_type = NetNet::REG;
4376 use_type = NetNet::IMPLICIT_REG;
4378 use_type = NetNet::IMPLICIT_REG;
4381 ptmp = pform_module_port_reference(name, @2.text, @2.first_line);
4382 pform_module_define_port(@2, name, NetNet::POUTPUT, use_type, $4, $1);
4383 port_declaration_context.port_type = NetNet::PINOUT;
4384 port_declaration_context.port_net_type = use_type;
4385 port_declaration_context.data_type = $4;
4387 pform_make_var_init(@5, name, $7);
4397 : net_type { $$ = $1; }
4398 | { $$ = NetNet::IMPLICIT; }
4402 * The signed_opt rule will return "true" if K_signed is present,
4403 * for "false" otherwise. This rule corresponds to the declaration
4404 * defaults for reg/bit/logic.
4406 * The signed_unsigned_opt rule with match K_signed or K_unsigned
4407 * and return true or false as appropriate. The default is
4408 * "true". This corresponds to the declaration defaults for
4409 * byte/shortint/int/longint.
4412 : K_signed { $$ = true; }
4413 | K_unsigned { $$ = false; }
4418 : K_signed { $$ = true; }
4419 | K_unsigned { $$ = false; }
4424 * In some places we can take any of the 4 2-value atom-type
4425 * names. All the context needs to know if that type is its width.
4428 : K_byte { $$ = 8; }
4429 | K_shortint { $$ = 16; }
4430 | K_int { $$ = 32; }
4431 | K_longint { $$ = 64; }
4434 /* An lpvalue is the expression that can go on the left side of a
4435 procedural assignment. This rule handles only procedural
4436 assignments. It is more limited than the general expr_primary
4437 rule to reflect the rules for assignment l-values. */
4439 : hierarchy_identifier
4440 { PEIdent*tmp = pform_new_ident(*$1);
4446 | implicit_class_handle '.' hierarchy_identifier
4447 { pform_name_t*t_name = $1;
4448 while (!$3->empty()) {
4449 t_name->push_back($3->front());
4452 PEIdent*tmp = new PEIdent(*t_name);
4459 | '{' expression_list_proper '}'
4460 { PEConcat*tmp = new PEConcat(*$2);
4466 | streaming_concatenation
4467 { yyerror(@1, "sorry: streaming concatenation not supported in l-values.");
4473 /* Continuous assignments have a list of individual assignments. */
4476 : lpvalue '=' expression
4477 { list<PExpr*>*tmp = new list<PExpr*>;
4485 : cont_assign_list ',' cont_assign
4486 { list<PExpr*>*tmp = $1;
4487 tmp->splice(tmp->end(), *$3);
4495 /* This is the global structure of a module. A module is a start
4496 section, with optional ports, then an optional list of module
4497 items, and finally an end marker. */
4500 : attribute_list_opt module_start lifetime_opt IDENTIFIER
4501 { pform_startmodule(@2, $4, $2==K_program, $2==K_interface, $3, $1); }
4502 module_package_import_list_opt
4503 module_parameter_port_list_opt
4504 module_port_list_opt
4505 module_attribute_foreign ';'
4506 { pform_module_set_ports($8); }
4507 timeunits_declaration_opt
4508 { pform_set_scope_timescale(@2); }
4509 module_item_list_opt
4511 { Module::UCDriveType ucd;
4512 // The lexor detected `unconnected_drive directives and
4513 // marked what it found in the uc_drive variable. Use that
4514 // to generate a UCD flag for the module.
4518 ucd = Module::UCD_NONE;
4521 ucd = Module::UCD_PULL0;
4524 ucd = Module::UCD_PULL1;
4527 // Check that program/endprogram and module/endmodule
4532 yyerror(@15, "error: module not closed by endmodule.");
4535 yyerror(@15, "error: program not closed by endprogram.");
4538 yyerror(@15, "error: interface not closed by endinterface.");
4544 pform_endmodule($4, in_celldefine, ucd);
4547 { // Last step: check any closing name. This is done late so
4548 // that the parser can look ahead to detect the present
4549 // endlabel_opt but still have the pform_endmodule() called
4550 // early enough that the lexor can know we are outside the
4553 if (strcmp($4,$17) != 0) {
4556 yyerror(@17, "error: End label doesn't match "
4560 yyerror(@17, "error: End label doesn't match "
4564 yyerror(@17, "error: End label doesn't match "
4571 if (($2 == K_module) && (! gn_system_verilog())) {
4572 yyerror(@8, "error: Module end labels require "
4581 /* Modules start with a module/macromodule, program, or interface
4582 keyword, and end with a endmodule, endprogram, or endinterface
4583 keyword. The syntax for modules programs, and interfaces is
4584 almost identical, so let semantics sort out the differences. */
4586 : K_module { $$ = K_module; }
4587 | K_macromodule { $$ = K_module; }
4588 | K_program { $$ = K_program; }
4589 | K_interface { $$ = K_interface; }
4593 : K_endmodule { $$ = K_module; }
4594 | K_endprogram { $$ = K_program; }
4595 | K_endinterface { $$ = K_interface; }
4599 : ':' IDENTIFIER { $$ = $2; }
4603 module_attribute_foreign
4604 : K_PSTAR IDENTIFIER K_integer IDENTIFIER '=' STRING ';' K_STARP { $$ = 0; }
4608 module_port_list_opt
4609 : '(' list_of_ports ')' { $$ = $2; }
4610 | '(' list_of_port_declarations ')' { $$ = $2; }
4613 { yyerror(@2, "Errors in port declarations.");
4619 /* Module declarations include optional ANSI style module parameter
4620 ports. These are simply advance ways to declare parameters, so
4621 that the port declarations may use them. */
4622 module_parameter_port_list_opt
4624 | '#' '(' module_parameter_port_list ')'
4627 module_parameter_port_list
4628 : K_parameter param_type parameter_assign
4629 | module_parameter_port_list ',' parameter_assign
4630 | module_parameter_port_list ',' K_parameter param_type parameter_assign
4635 /* Modules can contain further sub-module definitions. */
4638 | attribute_list_opt net_type data_type_or_implicit delay3_opt net_variable_list ';'
4640 { data_type_t*data_type = $3;
4641 if (data_type == 0) {
4642 data_type = new vector_type_t(IVL_VT_LOGIC, false, 0);
4643 FILE_NAME(data_type, @2);
4645 pform_set_data_type(@2, data_type, $5, $2, $1);
4647 yyerror(@2, "sorry: net delays not supported.");
4653 | attribute_list_opt K_wreal delay3 net_variable_list ';'
4654 { real_type_t*tmpt = new real_type_t(real_type_t::REAL);
4655 pform_set_data_type(@2, tmpt, $4, NetNet::WIRE, $1);
4657 yyerror(@3, "sorry: net delays not supported.");
4663 | attribute_list_opt K_wreal net_variable_list ';'
4664 { real_type_t*tmpt = new real_type_t(real_type_t::REAL);
4665 pform_set_data_type(@2, tmpt, $3, NetNet::WIRE, $1);
4669 /* Very similar to the rule above, but this takes a list of
4670 net_decl_assigns, which are <name> = <expr> assignment
4673 | attribute_list_opt net_type data_type_or_implicit delay3_opt net_decl_assigns ';'
4674 { data_type_t*data_type = $3;
4675 if (data_type == 0) {
4676 data_type = new vector_type_t(IVL_VT_LOGIC, false, 0);
4677 FILE_NAME(data_type, @2);
4679 pform_makewire(@2, $4, str_strength, $5, $2, data_type);
4681 yywarn(@2, "Attributes are not supported on net declaration "
4682 "assignments and will be discarded.");
4687 /* This form doesn't have the range, but does have strengths. This
4688 gives strength to the assignment drivers. */
4690 | attribute_list_opt net_type data_type_or_implicit drive_strength net_decl_assigns ';'
4691 { data_type_t*data_type = $3;
4692 if (data_type == 0) {
4693 data_type = new vector_type_t(IVL_VT_LOGIC, false, 0);
4694 FILE_NAME(data_type, @2);
4696 pform_makewire(@2, 0, $4, $5, $2, data_type);
4698 yywarn(@2, "Attributes are not supported on net declaration "
4699 "assignments and will be discarded.");
4704 | attribute_list_opt K_wreal net_decl_assigns ';'
4705 { real_type_t*data_type = new real_type_t(real_type_t::REAL);
4706 pform_makewire(@2, 0, str_strength, $3, NetNet::WIRE, data_type);
4708 yywarn(@2, "Attributes are not supported on net declaration "
4709 "assignments and will be discarded.");
4714 | K_trireg charge_strength_opt dimensions_opt delay3_opt list_of_identifiers ';'
4715 { yyerror(@1, "sorry: trireg nets not supported.");
4721 /* The next two rules handle port declarations that include a net type, e.g.
4722 input wire signed [h:l] <list>;
4723 This creates the wire and sets the port type all at once. */
4725 | attribute_list_opt port_direction net_type data_type_or_implicit list_of_port_identifiers ';'
4726 { pform_module_define_port(@2, $5, $2, $3, $4, $1); }
4728 | attribute_list_opt port_direction K_wreal list_of_port_identifiers ';'
4729 { real_type_t*real_type = new real_type_t(real_type_t::REAL);
4730 pform_module_define_port(@2, $4, $2, NetNet::WIRE, real_type, $1);
4733 /* The next three rules handle port declarations that include a variable
4735 output reg signed [h:l] <list>;
4736 and also handle incomplete port declarations, e.g.
4737 input signed [h:l] <list>;
4739 | attribute_list_opt K_inout data_type_or_implicit list_of_port_identifiers ';'
4740 { NetNet::Type use_type = $3 ? NetNet::IMPLICIT : NetNet::NONE;
4741 if (vector_type_t*dtype = dynamic_cast<vector_type_t*> ($3)) {
4742 if (dtype->implicit_flag)
4743 use_type = NetNet::NONE;
4745 if (use_type == NetNet::NONE)
4746 pform_set_port_type(@2, $4, NetNet::PINOUT, $3, $1);
4748 pform_module_define_port(@2, $4, NetNet::PINOUT, use_type, $3, $1);
4751 | attribute_list_opt K_input data_type_or_implicit list_of_port_identifiers ';'
4752 { NetNet::Type use_type = $3 ? NetNet::IMPLICIT : NetNet::NONE;
4753 if (vector_type_t*dtype = dynamic_cast<vector_type_t*> ($3)) {
4754 if (dtype->implicit_flag)
4755 use_type = NetNet::NONE;
4757 if (use_type == NetNet::NONE)
4758 pform_set_port_type(@2, $4, NetNet::PINPUT, $3, $1);
4760 pform_module_define_port(@2, $4, NetNet::PINPUT, use_type, $3, $1);
4763 | attribute_list_opt K_output data_type_or_implicit list_of_variable_port_identifiers ';'
4764 { NetNet::Type use_type = $3 ? NetNet::IMPLICIT : NetNet::NONE;
4765 if (vector_type_t*dtype = dynamic_cast<vector_type_t*> ($3)) {
4766 if (dtype->implicit_flag)
4767 use_type = NetNet::NONE;
4768 else if (dtype->reg_flag)
4769 use_type = NetNet::REG;
4771 use_type = NetNet::IMPLICIT_REG;
4773 // The SystemVerilog types that can show up as
4774 // output ports are implicitly (on the inside)
4775 // variables because "reg" is not valid syntax
4777 } else if (dynamic_cast<atom2_type_t*> ($3)) {
4778 use_type = NetNet::IMPLICIT_REG;
4779 } else if (dynamic_cast<struct_type_t*> ($3)) {
4780 use_type = NetNet::IMPLICIT_REG;
4781 } else if (enum_type_t*etype = dynamic_cast<enum_type_t*> ($3)) {
4782 if(etype->base_type == IVL_VT_LOGIC)
4783 use_type = NetNet::IMPLICIT_REG;
4785 if (use_type == NetNet::NONE)
4786 pform_set_port_type(@2, $4, NetNet::POUTPUT, $3, $1);
4788 pform_module_define_port(@2, $4, NetNet::POUTPUT, use_type, $3, $1);
4791 | attribute_list_opt port_direction net_type data_type_or_implicit error ';'
4792 { yyerror(@2, "error: Invalid variable list in port declaration.");
4798 | attribute_list_opt K_inout data_type_or_implicit error ';'
4799 { yyerror(@2, "error: Invalid variable list in port declaration.");
4805 | attribute_list_opt K_input data_type_or_implicit error ';'
4806 { yyerror(@2, "error: Invalid variable list in port declaration.");
4812 | attribute_list_opt K_output data_type_or_implicit error ';'
4813 { yyerror(@2, "error: Invalid variable list in port declaration.");
4819 /* Maybe this is a discipline declaration? If so, then the lexor
4820 will see the discipline name as an identifier. We match it to the
4821 discipline or type name semantically. */
4822 | DISCIPLINE_IDENTIFIER list_of_identifiers ';'
4823 { pform_attach_discipline(@1, $1, $2); }
4825 /* block_item_decl rule is shared with task blocks and named
4826 begin/end. Careful to pass attributes to the block_item_decl. */
4828 | attribute_list_opt { attributes_in_context = $1; } block_item_decl
4829 { delete attributes_in_context;
4830 attributes_in_context = 0;
4836 { if (pform_in_interface())
4837 yyerror(@1, "error: Parameter overrides are not allowed "
4840 defparam_assign_list ';'
4842 /* Most gate types have an optional drive strength and optional
4843 two/three-value delay. These rules handle the different cases.
4844 We check that the actual number of delays is correct later. */
4846 | attribute_list_opt gatetype gate_instance_list ';'
4847 { pform_makegates(@2, $2, str_strength, 0, $3, $1); }
4849 | attribute_list_opt gatetype delay3 gate_instance_list ';'
4850 { pform_makegates(@2, $2, str_strength, $3, $4, $1); }
4852 | attribute_list_opt gatetype drive_strength gate_instance_list ';'
4853 { pform_makegates(@2, $2, $3, 0, $4, $1); }
4855 | attribute_list_opt gatetype drive_strength delay3 gate_instance_list ';'
4856 { pform_makegates(@2, $2, $3, $4, $5, $1); }
4858 /* The switch type gates do not support a strength. */
4859 | attribute_list_opt switchtype gate_instance_list ';'
4860 { pform_makegates(@2, $2, str_strength, 0, $3, $1); }
4862 | attribute_list_opt switchtype delay3 gate_instance_list ';'
4863 { pform_makegates(@2, $2, str_strength, $3, $4, $1); }
4865 /* Pullup and pulldown devices cannot have delays, and their
4866 strengths are limited. */
4868 | K_pullup gate_instance_list ';'
4869 { pform_makegates(@1, PGBuiltin::PULLUP, pull_strength, 0, $2, 0); }
4870 | K_pulldown gate_instance_list ';'
4871 { pform_makegates(@1, PGBuiltin::PULLDOWN, pull_strength, 0, $2, 0); }
4873 | K_pullup '(' dr_strength1 ')' gate_instance_list ';'
4874 { pform_makegates(@1, PGBuiltin::PULLUP, $3, 0, $5, 0); }
4876 | K_pullup '(' dr_strength1 ',' dr_strength0 ')' gate_instance_list ';'
4877 { pform_makegates(@1, PGBuiltin::PULLUP, $3, 0, $7, 0); }
4879 | K_pullup '(' dr_strength0 ',' dr_strength1 ')' gate_instance_list ';'
4880 { pform_makegates(@1, PGBuiltin::PULLUP, $5, 0, $7, 0); }
4882 | K_pulldown '(' dr_strength0 ')' gate_instance_list ';'
4883 { pform_makegates(@1, PGBuiltin::PULLDOWN, $3, 0, $5, 0); }
4885 | K_pulldown '(' dr_strength1 ',' dr_strength0 ')' gate_instance_list ';'
4886 { pform_makegates(@1, PGBuiltin::PULLDOWN, $5, 0, $7, 0); }
4888 | K_pulldown '(' dr_strength0 ',' dr_strength1 ')' gate_instance_list ';'
4889 { pform_makegates(@1, PGBuiltin::PULLDOWN, $3, 0, $7, 0); }
4891 /* This rule handles instantiations of modules and user defined
4892 primitives. These devices to not have delay lists or strengths,
4893 but then can have parameter lists. */
4895 | attribute_list_opt
4896 IDENTIFIER parameter_value_opt gate_instance_list ';'
4897 { perm_string tmp1 = lex_strings.make($2);
4898 pform_make_modgates(@2, tmp1, $3, $4, $1);
4902 | attribute_list_opt
4903 IDENTIFIER parameter_value_opt error ';'
4904 { yyerror(@2, "error: Invalid module instantiation");
4909 /* Continuous assignment can have an optional drive strength, then
4910 an optional delay3 that applies to all the assignments in the
4911 cont_assign_list. */
4913 | K_assign drive_strength_opt delay3_opt cont_assign_list ';'
4914 { pform_make_pgassign_list($4, $3, $2, @1.text, @1.first_line); }
4916 /* Always and initial items are behavioral processes. */
4918 | attribute_list_opt K_always statement_item
4919 { PProcess*tmp = pform_make_behavior(IVL_PR_ALWAYS, $3, $1);
4922 | attribute_list_opt K_always_comb statement_item
4923 { PProcess*tmp = pform_make_behavior(IVL_PR_ALWAYS_COMB, $3, $1);
4926 | attribute_list_opt K_always_ff statement_item
4927 { PProcess*tmp = pform_make_behavior(IVL_PR_ALWAYS_FF, $3, $1);
4930 | attribute_list_opt K_always_latch statement_item
4931 { PProcess*tmp = pform_make_behavior(IVL_PR_ALWAYS_LATCH, $3, $1);
4934 | attribute_list_opt K_initial statement_item
4935 { PProcess*tmp = pform_make_behavior(IVL_PR_INITIAL, $3, $1);
4938 | attribute_list_opt K_final statement_item
4939 { PProcess*tmp = pform_make_behavior(IVL_PR_FINAL, $3, $1);
4943 | attribute_list_opt K_analog analog_statement
4944 { pform_make_analog_behavior(@2, IVL_PR_ALWAYS, $3); }
4946 | attribute_list_opt assertion_item
4948 | timeunits_declaration
4954 | function_declaration
4956 /* A generate region can contain further module items. Actually, it
4957 is supposed to be limited to certain kinds of module items, but
4958 the semantic tests will check that for us. Do check that the
4959 generate/endgenerate regions do not nest. Generate schemes nest,
4960 but generate regions do not. */
4962 | K_generate generate_item_list_opt K_endgenerate
4963 { // Test for bad nesting. I understand it, but it is illegal.
4964 if (pform_parent_generate()) {
4965 cerr << @1 << ": error: Generate/endgenerate regions cannot nest." << endl;
4966 cerr << @1 << ": : Try removing optional generate/endgenerate keywords," << endl;
4967 cerr << @1 << ": : or move them to surround the parent generate scheme." << endl;
4972 | K_genvar list_of_identifiers ';'
4973 { pform_genvars(@1, $2); }
4975 | K_for '(' IDENTIFIER '=' expression ';'
4977 IDENTIFIER '=' expression ')'
4978 { pform_start_generate_for(@1, $3, $5, $7, $9, $11); }
4980 { pform_endgenerate(); }
4985 { pform_start_generate_else(@1); }
4987 { pform_endgenerate(); }
4990 generate_block_opt %prec less_than_K_else
4991 { pform_endgenerate(); }
4993 | K_case '(' expression ')'
4994 { pform_start_generate_case(@1, $3); }
4997 { pform_endgenerate(); }
4999 | modport_declaration
5001 | package_import_declaration
5003 /* 1364-2001 and later allow specparam declarations outside specify blocks. */
5005 | attribute_list_opt K_specparam
5006 { if (pform_in_interface())
5007 yyerror(@1, "error: specparam declarations are not allowed "
5012 /* specify blocks are parsed but ignored. */
5015 { if (pform_in_interface())
5016 yyerror(@1, "error: specify blocks are not allowed "
5019 specify_item_list_opt K_endspecify
5021 | K_specify error K_endspecify
5022 { yyerror(@1, "error: syntax error in specify block");
5026 /* These rules match various errors that the user can type into
5027 module items. These rules try to catch them at a point where a
5028 reasonable error message can be produced. */
5031 { yyerror(@2, "error: invalid module item.");
5035 | K_assign error '=' expression ';'
5036 { yyerror(@1, "error: syntax error in left side "
5037 "of continuous assignment.");
5041 | K_assign error ';'
5042 { yyerror(@1, "error: syntax error in "
5043 "continuous assignment");
5047 | K_function error K_endfunction endlabel_opt
5048 { yyerror(@1, "error: I give up on this "
5049 "function definition.");
5051 if (!gn_system_verilog()) {
5052 yyerror(@4, "error: Function end names require "
5060 /* These rules are for the Icarus Verilog specific $attribute
5061 extensions. Then catch the parameters of the $attribute keyword. */
5063 | KK_attribute '(' IDENTIFIER ',' STRING ',' STRING ')' ';'
5064 { perm_string tmp3 = lex_strings.make($3);
5065 perm_string tmp5 = lex_strings.make($5);
5066 pform_set_attrib(tmp3, tmp5, $7);
5070 | KK_attribute '(' error ')' ';'
5071 { yyerror(@1, "error: Malformed $attribute parameter list."); }
5076 : module_item_list module_item
5080 module_item_list_opt
5085 generate_if : K_if '(' expression ')' { pform_start_generate_if(@1, $3); } ;
5088 : generate_case_items generate_case_item
5089 | generate_case_item
5093 : expression_list_proper ':' { pform_generate_case_item(@1, $1); } generate_block_opt
5094 { pform_endgenerate(); }
5095 | K_default ':' { pform_generate_case_item(@1, 0); } generate_block_opt
5096 { pform_endgenerate(); }
5101 /* Handle some anachronistic syntax cases. */
5102 | K_begin generate_item_list_opt K_end
5103 { /* Detect and warn about anachronistic begin/end use */
5104 if (generation_flag > GN_VER2001 && warn_anachronisms) {
5106 cerr << @1 << ": warning: Anachronistic use of begin/end to surround generate schemes." << endl;
5109 | K_begin ':' IDENTIFIER {
5110 pform_start_generate_nblock(@1, $3);
5111 } generate_item_list_opt K_end
5112 { /* Detect and warn about anachronistic named begin/end use */
5113 if (generation_flag > GN_VER2001 && warn_anachronisms) {
5115 cerr << @1 << ": warning: Anachronistic use of named begin/end to surround generate schemes." << endl;
5117 pform_endgenerate();
5122 : generate_item_list generate_item
5126 generate_item_list_opt
5127 : generate_item_list
5131 /* A generate block is the thing within a generate scheme. It may be
5132 a single module item, an anonymous block of module items, or a
5133 named module item. In all cases, the meat is in the module items
5134 inside, and the processing is done by the module_item rules. We
5135 only need to take note here of the scope name, if any. */
5139 | K_begin generate_item_list_opt K_end
5140 | K_begin ':' IDENTIFIER generate_item_list_opt K_end endlabel_opt
5141 { pform_generate_block_name($3);
5143 if (strcmp($3,$6) != 0) {
5144 yyerror(@6, "error: End label doesn't match "
5147 if (! gn_system_verilog()) {
5148 yyerror(@6, "error: Begin end labels require "
5157 generate_block_opt : generate_block | ';' ;
5160 /* A net declaration assignment allows the programmer to combine the
5161 net declaration and the continuous assignment into a single
5164 Note that the continuous assignment statement is generated as a
5165 side effect, and all I pass up is the name of the l-value. */
5168 : IDENTIFIER '=' expression
5169 { net_decl_assign_t*tmp = new net_decl_assign_t;
5171 tmp->name = lex_strings.make($1);
5179 : net_decl_assigns ',' net_decl_assign
5180 { net_decl_assign_t*tmp = $1;
5181 $3->next = tmp->next;
5191 : K_logic { $$ = IVL_VT_LOGIC; }
5192 | K_bool { $$ = IVL_VT_BOOL; /* Icarus misc */}
5193 | K_bit { $$ = IVL_VT_BOOL; /* IEEE1800 / IEEE1364-2009 */}
5198 | { $$ = IVL_VT_NO_TYPE; }
5202 : K_wire { $$ = NetNet::WIRE; }
5203 | K_tri { $$ = NetNet::TRI; }
5204 | K_tri1 { $$ = NetNet::TRI1; }
5205 | K_supply0 { $$ = NetNet::SUPPLY0; }
5206 | K_wand { $$ = NetNet::WAND; }
5207 | K_triand { $$ = NetNet::TRIAND; }
5208 | K_tri0 { $$ = NetNet::TRI0; }
5209 | K_supply1 { $$ = NetNet::SUPPLY1; }
5210 | K_wor { $$ = NetNet::WOR; }
5211 | K_trior { $$ = NetNet::TRIOR; }
5212 | K_wone { $$ = NetNet::UNRESOLVED_WIRE;
5213 cerr << @1.text << ":" << @1.first_line << ": warning: "
5214 "'wone' is deprecated, please use 'uwire' "
5217 | K_uwire { $$ = NetNet::UNRESOLVED_WIRE; }
5221 : bit_logic_opt unsigned_signed_opt dimensions_opt
5222 { param_active_range = $3;
5223 param_active_signed = $2;
5224 if (($1 == IVL_VT_NO_TYPE) && ($3 != 0))
5225 param_active_type = IVL_VT_LOGIC;
5227 param_active_type = $1;
5230 { param_active_range = make_range_from_width(integer_width);
5231 param_active_signed = true;
5232 param_active_type = IVL_VT_LOGIC;
5235 { param_active_range = make_range_from_width(64);
5236 param_active_signed = false;
5237 param_active_type = IVL_VT_LOGIC;
5240 { param_active_range = 0;
5241 param_active_signed = true;
5242 param_active_type = IVL_VT_REAL;
5245 { param_active_range = make_range_from_width($1);
5246 param_active_signed = true;
5247 param_active_type = IVL_VT_BOOL;
5250 { pform_set_param_from_type(@1, $1.type, $1.text, param_active_range,
5251 param_active_signed, param_active_type);
5256 /* parameter and localparam assignment lists are broken into
5257 separate BNF so that I can call slightly different parameter
5258 handling code. localparams parse the same as parameters, they
5259 just behave differently when someone tries to override them. */
5261 parameter_assign_list
5263 | parameter_assign_list ',' parameter_assign
5266 localparam_assign_list
5268 | localparam_assign_list ',' localparam_assign
5272 : IDENTIFIER '=' expression parameter_value_ranges_opt
5274 pform_set_parameter(@1, lex_strings.make($1), param_active_type,
5275 param_active_signed, param_active_range, tmp, $4);
5281 : IDENTIFIER '=' expression
5283 pform_set_localparam(@1, lex_strings.make($1), param_active_type,
5284 param_active_signed, param_active_range, tmp);
5289 parameter_value_ranges_opt : parameter_value_ranges { $$ = $1; } | { $$ = 0; } ;
5291 parameter_value_ranges
5292 : parameter_value_ranges parameter_value_range
5293 { $$ = $2; $$->next = $1; }
5294 | parameter_value_range
5295 { $$ = $1; $$->next = 0; }
5298 parameter_value_range
5299 : from_exclude '[' value_range_expression ':' value_range_expression ']'
5300 { $$ = pform_parameter_value_range($1, false, $3, false, $5); }
5301 | from_exclude '[' value_range_expression ':' value_range_expression ')'
5302 { $$ = pform_parameter_value_range($1, false, $3, true, $5); }
5303 | from_exclude '(' value_range_expression ':' value_range_expression ']'
5304 { $$ = pform_parameter_value_range($1, true, $3, false, $5); }
5305 | from_exclude '(' value_range_expression ':' value_range_expression ')'
5306 { $$ = pform_parameter_value_range($1, true, $3, true, $5); }
5307 | K_exclude expression
5308 { $$ = pform_parameter_value_range(true, false, $2, false, $2); }
5311 value_range_expression
5312 : expression { $$ = $1; }
5314 | '+' K_inf { $$ = 0; }
5315 | '-' K_inf { $$ = 0; }
5318 from_exclude : K_from { $$ = false; } | K_exclude { $$ = true; } ;
5320 /* The parameters of a module instance can be overridden by writing
5321 a list of expressions in a syntax much like a delay list. (The
5322 difference being the list can have any length.) The pform that
5323 attaches the expression list to the module checks that the
5324 expressions are constant.
5326 Although the BNF in IEEE1364-1995 implies that parameter value
5327 lists must be in parentheses, in practice most compilers will
5328 accept simple expressions outside of parentheses if there is only
5329 one value, so I'll accept simple numbers here. This also catches
5330 the case of a UDP with a single delay value, so we need to accept
5331 real values as well as decimal ones.
5333 The parameter value by name syntax is OVI enhancement BTF-B06 as
5334 approved by WG1364 on 6/28/1998. */
5337 : '#' '(' expression_list_with_nuls ')'
5338 { struct parmvalue_t*tmp = new struct parmvalue_t;
5343 | '#' '(' parameter_value_byname_list ')'
5344 { struct parmvalue_t*tmp = new struct parmvalue_t;
5351 PENumber*tmp = new PENumber($2);
5354 struct parmvalue_t*lst = new struct parmvalue_t;
5355 lst->by_order = new list<PExpr*>;
5356 lst->by_order->push_back(tmp);
5363 PEFNumber*tmp = new PEFNumber($2);
5366 struct parmvalue_t*lst = new struct parmvalue_t;
5367 lst->by_order = new list<PExpr*>;
5368 lst->by_order->push_back(tmp);
5373 { yyerror(@1, "error: syntax error in parameter value "
5374 "assignment list.");
5381 parameter_value_byname
5382 : '.' IDENTIFIER '(' expression ')'
5383 { named_pexpr_t*tmp = new named_pexpr_t;
5384 tmp->name = lex_strings.make($2);
5389 | '.' IDENTIFIER '(' ')'
5390 { named_pexpr_t*tmp = new named_pexpr_t;
5391 tmp->name = lex_strings.make($2);
5398 parameter_value_byname_list
5399 : parameter_value_byname
5400 { list<named_pexpr_t>*tmp = new list<named_pexpr_t>;
5401 tmp->push_back(*$1);
5405 | parameter_value_byname_list ',' parameter_value_byname
5406 { list<named_pexpr_t>*tmp = $1;
5407 tmp->push_back(*$3);
5414 /* The port (of a module) is a fairly complex item. Each port is
5415 handled as a Module::port_t object. A simple port reference has a
5416 name and a PExpr object, but more complex constructs are possible
5417 where the name can be attached to a list of PWire objects.
5419 The port_reference returns a Module::port_t, and so does the
5420 port_reference_list. The port_reference_list may have built up a
5421 list of PWires in the port_t object, but it is still a single
5422 Module::port_t object.
5424 The port rule below takes the built up Module::port_t object and
5425 tweaks its name as needed. */
5431 /* This syntax attaches an external name to the port reference so
5432 that the caller can bind by name to non-trivial port
5433 references. The port_t object gets its PWire from the
5434 port_reference, but its name from the IDENTIFIER. */
5436 | '.' IDENTIFIER '(' port_reference ')'
5437 { Module::port_t*tmp = $4;
5438 tmp->name = lex_strings.make($2);
5443 /* A port can also be a concatenation of port references. In this
5444 case the port does not have a name available to the outside, only
5445 positional parameter passing is possible here. */
5447 | '{' port_reference_list '}'
5448 { Module::port_t*tmp = $2;
5449 tmp->name = perm_string();
5453 /* This attaches a name to a port reference concatenation list so
5454 that parameter passing be name is possible. */
5456 | '.' IDENTIFIER '(' '{' port_reference_list '}' ')'
5457 { Module::port_t*tmp = $5;
5458 tmp->name = lex_strings.make($2);
5469 /* The port_name rule is used with a module is being *instantiated*,
5470 and not when it is being declared. See the port rule if you are
5471 looking for the ports of a module declaration. */
5474 : '.' IDENTIFIER '(' expression ')'
5475 { named_pexpr_t*tmp = new named_pexpr_t;
5476 tmp->name = lex_strings.make($2);
5481 | '.' IDENTIFIER '(' error ')'
5482 { yyerror(@3, "error: invalid port connection expression.");
5483 named_pexpr_t*tmp = new named_pexpr_t;
5484 tmp->name = lex_strings.make($2);
5489 | '.' IDENTIFIER '(' ')'
5490 { named_pexpr_t*tmp = new named_pexpr_t;
5491 tmp->name = lex_strings.make($2);
5497 { named_pexpr_t*tmp = new named_pexpr_t;
5498 tmp->name = lex_strings.make($2);
5499 tmp->parm = new PEIdent(lex_strings.make($2), true);
5500 FILE_NAME(tmp->parm, @1);
5505 { named_pexpr_t*tmp = new named_pexpr_t;
5506 tmp->name = lex_strings.make("*");
5513 : port_name_list ',' port_name
5514 { list<named_pexpr_t>*tmp = $1;
5515 tmp->push_back(*$3);
5520 { list<named_pexpr_t>*tmp = new list<named_pexpr_t>;
5521 tmp->push_back(*$1);
5528 /* A port reference is an internal (to the module) name of the port,
5529 possibly with a part of bit select to attach it to specific bits
5530 of a signal fully declared inside the module.
5532 The parser creates a PEIdent for every port reference, even if the
5533 signal is bound to different ports. The elaboration figures out
5534 the mess that this creates. The port_reference (and the
5535 port_reference_list below) puts the port reference PEIdent into the
5536 port_t object to pass it up to the module declaration code. */
5541 { Module::port_t*ptmp;
5542 perm_string name = lex_strings.make($1);
5543 ptmp = pform_module_port_reference(name, @1.text, @1.first_line);
5548 | IDENTIFIER '[' expression ':' expression ']'
5549 { index_component_t itmp;
5550 itmp.sel = index_component_t::SEL_PART;
5554 name_component_t ntmp (lex_strings.make($1));
5555 ntmp.index.push_back(itmp);
5558 pname.push_back(ntmp);
5560 PEIdent*wtmp = new PEIdent(pname);
5561 FILE_NAME(wtmp, @1);
5563 Module::port_t*ptmp = new Module::port_t;
5564 ptmp->name = perm_string();
5565 ptmp->expr.push_back(wtmp);
5571 | IDENTIFIER '[' expression ']'
5572 { index_component_t itmp;
5573 itmp.sel = index_component_t::SEL_BIT;
5577 name_component_t ntmp (lex_strings.make($1));
5578 ntmp.index.push_back(itmp);
5581 pname.push_back(ntmp);
5583 PEIdent*tmp = new PEIdent(pname);
5586 Module::port_t*ptmp = new Module::port_t;
5587 ptmp->name = perm_string();
5588 ptmp->expr.push_back(tmp);
5593 | IDENTIFIER '[' error ']'
5594 { yyerror(@1, "error: invalid port bit select");
5595 Module::port_t*ptmp = new Module::port_t;
5596 PEIdent*wtmp = new PEIdent(lex_strings.make($1));
5597 FILE_NAME(wtmp, @1);
5598 ptmp->name = lex_strings.make($1);
5599 ptmp->expr.push_back(wtmp);
5609 | port_reference_list ',' port_reference
5610 { Module::port_t*tmp = $1;
5611 append(tmp->expr, $3->expr);
5617 /* The range is a list of variable dimensions. */
5620 | dimensions { $$ = $1; }
5624 : variable_dimension
5626 | dimensions variable_dimension
5627 { list<pform_range_t> *tmp = $1;
5629 tmp->splice(tmp->end(), *$2);
5636 /* The register_variable rule is matched only when I am parsing
5637 variables in a "reg" definition. I therefore know that I am
5638 creating registers and I do not need to let the containing rule
5639 handle it. The register variable list simply packs them together
5640 so that bit ranges can be assigned. */
5642 : IDENTIFIER dimensions_opt
5643 { perm_string name = lex_strings.make($1);
5644 pform_makewire(@1, name, NetNet::REG,
5645 NetNet::NOT_A_PORT, IVL_VT_NO_TYPE, 0);
5646 pform_set_reg_idx(name, $2);
5649 | IDENTIFIER dimensions_opt '=' expression
5650 { if (pform_peek_scope()->var_init_needs_explicit_lifetime()
5651 && (var_lifetime == LexicalScope::INHERITED)) {
5652 cerr << @3 << ": warning: Static variable initialization requires "
5653 "explicit lifetime in this context." << endl;
5656 perm_string name = lex_strings.make($1);
5657 pform_makewire(@1, name, NetNet::REG,
5658 NetNet::NOT_A_PORT, IVL_VT_NO_TYPE, 0);
5659 pform_set_reg_idx(name, $2);
5660 pform_make_var_init(@1, name, $4);
5665 register_variable_list
5667 { list<perm_string>*tmp = new list<perm_string>;
5668 tmp->push_back(lex_strings.make($1));
5672 | register_variable_list ',' register_variable
5673 { list<perm_string>*tmp = $1;
5674 tmp->push_back(lex_strings.make($3));
5681 : IDENTIFIER dimensions_opt
5682 { perm_string name = lex_strings.make($1);
5683 pform_makewire(@1, name, NetNet::IMPLICIT,
5684 NetNet::NOT_A_PORT, IVL_VT_NO_TYPE, 0);
5685 pform_set_reg_idx(name, $2);
5692 { list<perm_string>*tmp = new list<perm_string>;
5693 tmp->push_back(lex_strings.make($1));
5697 | net_variable_list ',' net_variable
5698 { list<perm_string>*tmp = $1;
5699 tmp->push_back(lex_strings.make($3));
5706 : IDENTIFIER dimensions_opt
5708 yyerror(@2, "sorry: event arrays are not supported.");
5717 { $$ = list_from_identifier($1); }
5718 | event_variable_list ',' event_variable
5719 { $$ = list_from_identifier($1, $3); }
5723 : K_specparam specparam_decl ';'
5724 | specify_simple_path_decl ';'
5725 { pform_module_specify_path($1);
5727 | specify_edge_path_decl ';'
5728 { pform_module_specify_path($1);
5730 | K_if '(' expression ')' specify_simple_path_decl ';'
5731 { PSpecPath*tmp = $5;
5733 tmp->conditional = true;
5734 tmp->condition = $3;
5736 pform_module_specify_path(tmp);
5738 | K_if '(' expression ')' specify_edge_path_decl ';'
5739 { PSpecPath*tmp = $5;
5741 tmp->conditional = true;
5742 tmp->condition = $3;
5744 pform_module_specify_path(tmp);
5746 | K_ifnone specify_simple_path_decl ';'
5747 { PSpecPath*tmp = $2;
5749 tmp->conditional = true;
5752 pform_module_specify_path(tmp);
5754 | K_ifnone specify_edge_path_decl ';'
5755 { yyerror(@1, "Sorry: ifnone with an edge-sensitive path is "
5759 | K_Sfullskew '(' spec_reference_event ',' spec_reference_event
5760 ',' delay_value ',' delay_value spec_notifier_opt ')' ';'
5764 | K_Shold '(' spec_reference_event ',' spec_reference_event
5765 ',' delay_value spec_notifier_opt ')' ';'
5768 | K_Snochange '(' spec_reference_event ',' spec_reference_event
5769 ',' delay_value ',' delay_value spec_notifier_opt ')' ';'
5773 | K_Speriod '(' spec_reference_event ',' delay_value
5774 spec_notifier_opt ')' ';'
5777 | K_Srecovery '(' spec_reference_event ',' spec_reference_event
5778 ',' delay_value spec_notifier_opt ')' ';'
5781 | K_Srecrem '(' spec_reference_event ',' spec_reference_event
5782 ',' delay_value ',' delay_value spec_notifier_opt ')' ';'
5786 | K_Sremoval '(' spec_reference_event ',' spec_reference_event
5787 ',' delay_value spec_notifier_opt ')' ';'
5790 | K_Ssetup '(' spec_reference_event ',' spec_reference_event
5791 ',' delay_value spec_notifier_opt ')' ';'
5794 | K_Ssetuphold '(' spec_reference_event ',' spec_reference_event
5795 ',' delay_value ',' delay_value spec_notifier_opt ')' ';'
5799 | K_Sskew '(' spec_reference_event ',' spec_reference_event
5800 ',' delay_value spec_notifier_opt ')' ';'
5803 | K_Stimeskew '(' spec_reference_event ',' spec_reference_event
5804 ',' delay_value spec_notifier_opt ')' ';'
5807 | K_Swidth '(' spec_reference_event ',' delay_value ',' expression
5808 spec_notifier_opt ')' ';'
5812 | K_Swidth '(' spec_reference_event ',' delay_value ')' ';'
5815 | K_pulsestyle_onevent specify_path_identifiers ';'
5818 | K_pulsestyle_ondetect specify_path_identifiers ';'
5821 | K_showcancelled specify_path_identifiers ';'
5824 | K_noshowcancelled specify_path_identifiers ';'
5831 | specify_item_list specify_item
5834 specify_item_list_opt
5840 specify_edge_path_decl
5841 : specify_edge_path '=' '(' delay_value_list ')'
5842 { $$ = pform_assign_path_delay($1, $4); }
5843 | specify_edge_path '=' delay_value_simple
5844 { list<PExpr*>*tmp = new list<PExpr*>;
5846 $$ = pform_assign_path_delay($1, tmp);
5850 edge_operator : K_posedge { $$ = true; } | K_negedge { $$ = false; } ;
5853 : '(' specify_path_identifiers spec_polarity
5854 K_EG '(' specify_path_identifiers polarity_operator expression ')' ')'
5855 { int edge_flag = 0;
5856 $$ = pform_make_specify_edge_path(@1, edge_flag, $2, $3, false, $6, $8); }
5857 | '(' edge_operator specify_path_identifiers spec_polarity
5858 K_EG '(' specify_path_identifiers polarity_operator expression ')' ')'
5859 { int edge_flag = $2? 1 : -1;
5860 $$ = pform_make_specify_edge_path(@1, edge_flag, $3, $4, false, $7, $9);}
5861 | '(' specify_path_identifiers spec_polarity
5862 K_SG '(' specify_path_identifiers polarity_operator expression ')' ')'
5863 { int edge_flag = 0;
5864 $$ = pform_make_specify_edge_path(@1, edge_flag, $2, $3, true, $6, $8); }
5865 | '(' edge_operator specify_path_identifiers spec_polarity
5866 K_SG '(' specify_path_identifiers polarity_operator expression ')' ')'
5867 { int edge_flag = $2? 1 : -1;
5868 $$ = pform_make_specify_edge_path(@1, edge_flag, $3, $4, true, $7, $9); }
5877 specify_simple_path_decl
5878 : specify_simple_path '=' '(' delay_value_list ')'
5879 { $$ = pform_assign_path_delay($1, $4); }
5880 | specify_simple_path '=' delay_value_simple
5881 { list<PExpr*>*tmp = new list<PExpr*>;
5883 $$ = pform_assign_path_delay($1, tmp);
5885 | specify_simple_path '=' '(' error ')'
5886 { yyerror(@3, "Syntax error in delay value list.");
5893 : '(' specify_path_identifiers spec_polarity
5894 K_EG specify_path_identifiers ')'
5895 { $$ = pform_make_specify_path(@1, $2, $3, false, $5); }
5896 | '(' specify_path_identifiers spec_polarity
5897 K_SG specify_path_identifiers ')'
5898 { $$ = pform_make_specify_path(@1, $2, $3, true, $5); }
5900 { yyerror(@1, "Invalid simple path");
5905 specify_path_identifiers
5907 { list<perm_string>*tmp = new list<perm_string>;
5908 tmp->push_back(lex_strings.make($1));
5912 | IDENTIFIER '[' expr_primary ']'
5913 { if (gn_specify_blocks_flag) {
5914 yywarn(@4, "Bit selects are not currently supported "
5915 "in path declarations. The declaration "
5916 "will be applied to the whole vector.");
5918 list<perm_string>*tmp = new list<perm_string>;
5919 tmp->push_back(lex_strings.make($1));
5923 | IDENTIFIER '[' expr_primary polarity_operator expr_primary ']'
5924 { if (gn_specify_blocks_flag) {
5925 yywarn(@4, "Part selects are not currently supported "
5926 "in path declarations. The declaration "
5927 "will be applied to the whole vector.");
5929 list<perm_string>*tmp = new list<perm_string>;
5930 tmp->push_back(lex_strings.make($1));
5934 | specify_path_identifiers ',' IDENTIFIER
5935 { list<perm_string>*tmp = $1;
5936 tmp->push_back(lex_strings.make($3));
5940 | specify_path_identifiers ',' IDENTIFIER '[' expr_primary ']'
5941 { if (gn_specify_blocks_flag) {
5942 yywarn(@4, "Bit selects are not currently supported "
5943 "in path declarations. The declaration "
5944 "will be applied to the whole vector.");
5946 list<perm_string>*tmp = $1;
5947 tmp->push_back(lex_strings.make($3));
5951 | specify_path_identifiers ',' IDENTIFIER '[' expr_primary polarity_operator expr_primary ']'
5952 { if (gn_specify_blocks_flag) {
5953 yywarn(@4, "Part selects are not currently supported "
5954 "in path declarations. The declaration "
5955 "will be applied to the whole vector.");
5957 list<perm_string>*tmp = $1;
5958 tmp->push_back(lex_strings.make($3));
5965 : IDENTIFIER '=' expression
5967 pform_set_specparam(@1, lex_strings.make($1),
5968 param_active_range, tmp);
5971 | IDENTIFIER '=' expression ':' expression ':' expression
5973 switch (min_typ_max_flag) {
5990 if (min_typ_max_warn > 0) {
5991 cerr << tmp->get_fileline() << ": warning: choosing ";
5992 switch (min_typ_max_flag) {
6003 cerr << " expression." << endl;
6004 min_typ_max_warn -= 1;
6006 pform_set_specparam(@1, lex_strings.make($1),
6007 param_active_range, tmp);
6010 | PATHPULSE_IDENTIFIER '=' expression
6014 | PATHPULSE_IDENTIFIER '=' '(' expression ',' expression ')'
6023 | specparam_list ',' specparam
6029 { param_active_range = $1; }
6031 { param_active_range = 0; }
6040 spec_reference_event
6041 : K_posedge expression
6043 | K_negedge expression
6045 | K_posedge expr_primary K_TAND expression
6049 | K_negedge expr_primary K_TAND expression
6053 | K_edge '[' edge_descriptor_list ']' expr_primary
6055 | K_edge '[' edge_descriptor_list ']' expr_primary K_TAND expression
6059 | expr_primary K_TAND expression
6067 /* The edge_descriptor is detected by the lexor as the various
6068 2-letter edge sequences that are supported here. For now, we
6069 don't care what they are, because we do not yet support specify
6071 edge_descriptor_list
6072 : edge_descriptor_list ',' K_edge_descriptor
6084 { args_after_notifier = 0; }
6085 | ',' hierarchy_identifier
6086 { args_after_notifier = 0; delete $2; }
6088 { args_after_notifier += 1; }
6089 | spec_notifier ',' hierarchy_identifier
6090 { args_after_notifier += 1;
6091 if (args_after_notifier >= 3) {
6092 cerr << @3 << ": warning: timing checks are not supported "
6093 "and delayed signal \"" << *$3
6094 << "\" will not be driven." << endl;
6097 /* How do we match this path? */
6099 { args_after_notifier = 0; delete[]$1; }
6103 statement_item /* This is roughly statement_item in the LRM */
6105 /* assign and deassign statements are procedural code to do
6106 structural assignments, and to turn that structural assignment
6107 off. This is stronger than any other assign, but weaker than the
6108 force assignments. */
6110 : K_assign lpvalue '=' expression ';'
6111 { PCAssign*tmp = new PCAssign($2, $4);
6116 | K_deassign lpvalue ';'
6117 { PDeassign*tmp = new PDeassign($2);
6123 /* Force and release statements are similar to assignments,
6124 syntactically, but they will be elaborated differently. */
6126 | K_force lpvalue '=' expression ';'
6127 { PForce*tmp = new PForce($2, $4);
6131 | K_release lpvalue ';'
6132 { PRelease*tmp = new PRelease($2);
6137 /* begin-end blocks come in a variety of forms, including named and
6138 anonymous. The named blocks can also carry their own reg
6139 variables, which are placed in the scope created by the block
6140 name. These are handled by pushing the scope name, then matching
6141 the declarations. The scope is popped at the end of the block. */
6144 { PBlock*tmp = new PBlock(PBlock::BL_SEQ);
6148 /* In SystemVerilog an unnamed block can contain variable declarations. */
6150 { PBlock*tmp = pform_push_block_scope(0, PBlock::BL_SEQ);
6152 current_block_stack.push(tmp);
6154 block_item_decls_opt
6156 if (! gn_system_verilog()) {
6157 yyerror("error: Variable declaration in unnamed block "
6158 "requires SystemVerilog.");
6161 /* If there are no declarations in the scope then just delete it. */
6163 assert(! current_block_stack.empty());
6164 PBlock*tmp = current_block_stack.top();
6165 current_block_stack.pop();
6169 statement_or_null_list K_end
6173 assert(! current_block_stack.empty());
6174 tmp = current_block_stack.top();
6175 current_block_stack.pop();
6177 tmp = new PBlock(PBlock::BL_SEQ);
6180 if ($5) tmp->set_statement(*$5);
6184 | K_begin ':' IDENTIFIER
6185 { PBlock*tmp = pform_push_block_scope($3, PBlock::BL_SEQ);
6187 current_block_stack.push(tmp);
6189 block_item_decls_opt
6190 statement_or_null_list_opt K_end endlabel_opt
6191 { pform_pop_scope();
6192 assert(! current_block_stack.empty());
6193 PBlock*tmp = current_block_stack.top();
6194 current_block_stack.pop();
6195 if ($6) tmp->set_statement(*$6);
6198 if (strcmp($3,$8) != 0) {
6199 yyerror(@8, "error: End label doesn't match begin name");
6201 if (! gn_system_verilog()) {
6202 yyerror(@8, "error: Begin end labels require "
6211 /* fork-join blocks are very similar to begin-end blocks. In fact,
6212 from the parser's perspective there is no real difference. All we
6213 need to do is remember that this is a parallel block so that the
6214 code generator can do the right thing. */
6216 | K_fork join_keyword
6217 { PBlock*tmp = new PBlock($2);
6221 /* In SystemVerilog an unnamed block can contain variable declarations. */
6223 { PBlock*tmp = pform_push_block_scope(0, PBlock::BL_PAR);
6225 current_block_stack.push(tmp);
6227 block_item_decls_opt
6229 if (! gn_system_verilog()) {
6230 yyerror("error: Variable declaration in unnamed block "
6231 "requires SystemVerilog.");
6234 /* If there are no declarations in the scope then just delete it. */
6236 assert(! current_block_stack.empty());
6237 PBlock*tmp = current_block_stack.top();
6238 current_block_stack.pop();
6242 statement_or_null_list join_keyword
6246 assert(! current_block_stack.empty());
6247 tmp = current_block_stack.top();
6248 current_block_stack.pop();
6249 tmp->set_join_type($6);
6251 tmp = new PBlock($6);
6254 if ($5) tmp->set_statement(*$5);
6258 | K_fork ':' IDENTIFIER
6259 { PBlock*tmp = pform_push_block_scope($3, PBlock::BL_PAR);
6261 current_block_stack.push(tmp);
6263 block_item_decls_opt
6264 statement_or_null_list_opt join_keyword endlabel_opt
6265 { pform_pop_scope();
6266 assert(! current_block_stack.empty());
6267 PBlock*tmp = current_block_stack.top();
6268 current_block_stack.pop();
6269 tmp->set_join_type($7);
6270 if ($6) tmp->set_statement(*$6);
6273 if (strcmp($3,$8) != 0) {
6274 yyerror(@8, "error: End label doesn't match fork name");
6276 if (! gn_system_verilog()) {
6277 yyerror(@8, "error: Fork end labels require "
6286 | K_disable hierarchy_identifier ';'
6287 { PDisable*tmp = new PDisable(*$2);
6292 | K_disable K_fork ';'
6293 { pform_name_t tmp_name;
6294 PDisable*tmp = new PDisable(tmp_name);
6298 | K_TRIGGER hierarchy_identifier ';'
6299 { PTrigger*tmp = new PTrigger(*$2);
6305 | procedural_assertion_statement { $$ = $1; }
6307 | loop_statement { $$ = $1; }
6309 | jump_statement { $$ = $1; }
6311 | K_case '(' expression ')' case_items K_endcase
6312 { PCase*tmp = new PCase(NetCase::EQ, $3, $5);
6316 | K_casex '(' expression ')' case_items K_endcase
6317 { PCase*tmp = new PCase(NetCase::EQX, $3, $5);
6321 | K_casez '(' expression ')' case_items K_endcase
6322 { PCase*tmp = new PCase(NetCase::EQZ, $3, $5);
6326 | K_case '(' expression ')' error K_endcase
6328 | K_casex '(' expression ')' error K_endcase
6330 | K_casez '(' expression ')' error K_endcase
6332 | K_if '(' expression ')' statement_or_null %prec less_than_K_else
6333 { PCondit*tmp = new PCondit($3, $5, 0);
6337 | K_if '(' expression ')' statement_or_null K_else statement_or_null
6338 { PCondit*tmp = new PCondit($3, $5, $7);
6342 | K_if '(' error ')' statement_or_null %prec less_than_K_else
6343 { yyerror(@1, "error: Malformed conditional expression.");
6346 | K_if '(' error ')' statement_or_null K_else statement_or_null
6347 { yyerror(@1, "error: Malformed conditional expression.");
6350 /* SystemVerilog adds the compressed_statement */
6352 | compressed_statement ';'
6355 /* increment/decrement expressions can also be statements. When used
6356 as statements, we can rewrite a++ as a += 1, and so on. */
6358 | inc_or_dec_expression ';'
6359 { $$ = pform_compressed_assign_from_inc_dec(@1, $1); }
6363 | delay1 statement_or_null
6364 { PExpr*del = $1->front();
6365 assert($1->size() == 1);
6367 PDelayStatement*tmp = new PDelayStatement(del, $2);
6372 | event_control statement_or_null
6373 { PEventStatement*tmp = $1;
6375 yyerror(@1, "error: Invalid event control.");
6378 tmp->set_statement($2);
6382 | '@' '*' statement_or_null
6383 { PEventStatement*tmp = new PEventStatement;
6385 tmp->set_statement($3);
6388 | '@' '(' '*' ')' statement_or_null
6389 { PEventStatement*tmp = new PEventStatement;
6391 tmp->set_statement($5);
6395 /* Various assignment statements */
6397 | lpvalue '=' expression ';'
6398 { PAssign*tmp = new PAssign($1,$3);
6403 | error '=' expression ';'
6404 { yyerror(@2, "Syntax in assignment statement l-value.");
6408 | lpvalue K_LE expression ';'
6409 { PAssignNB*tmp = new PAssignNB($1,$3);
6413 | error K_LE expression ';'
6414 { yyerror(@2, "Syntax in assignment statement l-value.");
6418 | lpvalue '=' delay1 expression ';'
6419 { PExpr*del = $3->front(); $3->pop_front();
6420 assert($3->empty());
6421 PAssign*tmp = new PAssign($1,del,$4);
6425 | lpvalue K_LE delay1 expression ';'
6426 { PExpr*del = $3->front(); $3->pop_front();
6427 assert($3->empty());
6428 PAssignNB*tmp = new PAssignNB($1,del,$4);
6432 | lpvalue '=' event_control expression ';'
6433 { PAssign*tmp = new PAssign($1,0,$3,$4);
6437 | lpvalue '=' K_repeat '(' expression ')' event_control expression ';'
6438 { PAssign*tmp = new PAssign($1,$5,$7,$8);
6440 tmp->set_lineno(@1.first_line);
6443 | lpvalue K_LE event_control expression ';'
6444 { PAssignNB*tmp = new PAssignNB($1,0,$3,$4);
6448 | lpvalue K_LE K_repeat '(' expression ')' event_control expression ';'
6449 { PAssignNB*tmp = new PAssignNB($1,$5,$7,$8);
6454 /* The IEEE1800 standard defines dynamic_array_new assignment as a
6455 different rule from regular assignment. That implies that the
6456 dynamic_array_new is not an expression in general, which makes
6457 some sense. Elaboration should make sure the lpvalue is an array name. */
6459 | lpvalue '=' dynamic_array_new ';'
6460 { PAssign*tmp = new PAssign($1,$3);
6465 /* The class new and dynamic array new expressions are special, so
6466 sit in rules of their own. */
6468 | lpvalue '=' class_new ';'
6469 { PAssign*tmp = new PAssign($1,$3);
6474 | K_wait '(' expression ')' statement_or_null
6475 { PEventStatement*tmp;
6476 PEEvent*etmp = new PEEvent(PEEvent::POSITIVE, $3);
6477 tmp = new PEventStatement(etmp);
6479 tmp->set_statement($5);
6483 { PEventStatement*tmp = new PEventStatement((PEEvent*)0);
6487 | SYSTEM_IDENTIFIER '(' expression_list_with_nuls ')' ';'
6488 { PCallTask*tmp = new PCallTask(lex_strings.make($1), *$3);
6494 | SYSTEM_IDENTIFIER ';'
6496 PCallTask*tmp = new PCallTask(lex_strings.make($1), pt);
6502 | hierarchy_identifier '(' expression_list_with_nuls ')' ';'
6503 { PCallTask*tmp = pform_make_call_task(@1, *$1, *$3);
6509 | hierarchy_identifier K_with '{' constraint_block_item_list_opt '}' ';'
6510 { /* ....randomize with { <constraints> } */
6511 if ($1 && peek_tail_name(*$1) == "randomize") {
6512 if (!gn_system_verilog())
6513 yyerror(@2, "error: Randomize with constraint requires SystemVerilog.");
6515 yyerror(@2, "sorry: Randomize with constraint not supported.");
6517 yyerror(@2, "error: Constraint block can only be applied to randomize method.");
6520 PCallTask*tmp = new PCallTask(*$1, pt);
6526 | implicit_class_handle '.' hierarchy_identifier '(' expression_list_with_nuls ')' ';'
6527 { pform_name_t*t_name = $1;
6528 while (! $3->empty()) {
6529 t_name->push_back($3->front());
6532 PCallTask*tmp = new PCallTask(*t_name, *$5);
6540 | hierarchy_identifier ';'
6542 PCallTask*tmp = pform_make_call_task(@1, *$1, pt);
6547 /* IEEE1800 A.1.8: class_constructor_declaration with a call to
6548 parent constructor. Note that the implicit_class_handle must
6549 be K_super ("this.new" makes little sense) but that would
6550 cause a conflict. Anyhow, this statement must be in the
6551 beginning of a constructor, but let the elaborator figure that
6554 | implicit_class_handle '.' K_new '(' expression_list_with_nuls ')' ';'
6555 { PChainConstructor*tmp = new PChainConstructor(*$5);
6560 | hierarchy_identifier '(' error ')' ';'
6561 { yyerror(@3, "error: Syntax error in task arguments.");
6563 PCallTask*tmp = pform_make_call_task(@1, *$1, pt);
6569 { yyerror(@2, "error: malformed statement");
6576 compressed_statement
6577 : lpvalue K_PLUS_EQ expression
6578 { PAssign*tmp = new PAssign($1, '+', $3);
6582 | lpvalue K_MINUS_EQ expression
6583 { PAssign*tmp = new PAssign($1, '-', $3);
6587 | lpvalue K_MUL_EQ expression
6588 { PAssign*tmp = new PAssign($1, '*', $3);
6592 | lpvalue K_DIV_EQ expression
6593 { PAssign*tmp = new PAssign($1, '/', $3);
6597 | lpvalue K_MOD_EQ expression
6598 { PAssign*tmp = new PAssign($1, '%', $3);
6602 | lpvalue K_AND_EQ expression
6603 { PAssign*tmp = new PAssign($1, '&', $3);
6607 | lpvalue K_OR_EQ expression
6608 { PAssign*tmp = new PAssign($1, '|', $3);
6612 | lpvalue K_XOR_EQ expression
6613 { PAssign*tmp = new PAssign($1, '^', $3);
6617 | lpvalue K_LS_EQ expression
6618 { PAssign *tmp = new PAssign($1, 'l', $3);
6622 | lpvalue K_RS_EQ expression
6623 { PAssign*tmp = new PAssign($1, 'r', $3);
6627 | lpvalue K_RSS_EQ expression
6628 { PAssign *tmp = new PAssign($1, 'R', $3);
6635 statement_or_null_list_opt
6636 : statement_or_null_list
6642 statement_or_null_list
6643 : statement_or_null_list statement_or_null
6644 { vector<Statement*>*tmp = $1;
6645 if ($2) tmp->push_back($2);
6649 { vector<Statement*>*tmp = new vector<Statement*>(0);
6650 if ($1) tmp->push_back($1);
6656 : branch_probe_expression K_CONTRIBUTE expression ';'
6657 { $$ = pform_contribution_statement(@2, $1, $3); }
6660 /* Task items are, other than the statement, task port items and
6661 other block items. */
6663 : block_item_decl { $$ = new vector<pform_tf_port_t>(0); }
6664 | tf_port_declaration { $$ = $1; }
6668 : task_item_list task_item
6669 { vector<pform_tf_port_t>*tmp = $1;
6670 size_t s1 = tmp->size();
6671 tmp->resize(s1 + $2->size());
6672 for (size_t idx = 0 ; idx < $2->size() ; idx += 1)
6673 tmp->at(s1 + idx) = $2->at(idx);
6689 : tf_port_list { $$ = $1; }
6693 /* Note that the lexor notices the "table" keyword and starts
6694 the UDPTABLE state. It needs to happen there so that all the
6695 characters in the table are interpreted in that mode. It is still
6696 up to this rule to take us out of the UDPTABLE state. */
6698 : K_table udp_entry_list K_endtable
6702 | K_table K_endtable
6704 yyerror(@1, "error: Empty UDP table.");
6707 | K_table error K_endtable
6709 yyerror(@2, "Errors in UDP table");
6716 : udp_comb_entry_list
6717 | udp_sequ_entry_list
6721 : udp_input_list ':' udp_output_sym ';'
6722 { char*tmp = new char[strlen($1)+3];
6724 char*tp = tmp+strlen(tmp);
6735 { list<string>*tmp = new list<string>;
6740 | udp_comb_entry_list udp_comb_entry
6741 { list<string>*tmp = $1;
6750 { list<string>*tmp = new list<string>;
6755 | udp_sequ_entry_list udp_sequ_entry
6756 { list<string>*tmp = $1;
6764 : udp_input_list ':' udp_input_sym ':' udp_output_sym ';'
6765 { char*tmp = new char[strlen($1)+5];
6767 char*tp = tmp+strlen(tmp);
6778 : K_initial IDENTIFIER '=' number ';'
6779 { PExpr*etmp = new PENumber($4);
6780 PEIdent*itmp = new PEIdent(lex_strings.make($2));
6781 PAssign*atmp = new PAssign(itmp, etmp);
6782 FILE_NAME(atmp, @2);
6789 : udp_initial { $$ = $1; }
6795 { char*tmp = new char[2];
6800 | udp_input_list udp_input_sym
6801 { char*tmp = new char[strlen($1)+2];
6803 char*tp = tmp+strlen(tmp);
6835 | DEC_NUMBER { yyerror(@1, "internal error: Input digits parse as decimal number!"); $$ = '0'; }
6843 | DEC_NUMBER { yyerror(@1, "internal error: Output digits parse as decimal number!"); $$ = '0'; }
6846 /* Port declarations create wires for the inputs and the output. The
6847 makes for these ports are scoped within the UDP, so there is no
6848 hierarchy involved. */
6850 : K_input list_of_identifiers ';'
6851 { $$ = pform_make_udp_input_ports($2); }
6852 | K_output IDENTIFIER ';'
6853 { perm_string pname = lex_strings.make($2);
6854 PWire*pp = new PWire(pname, NetNet::IMPLICIT, NetNet::POUTPUT, IVL_VT_LOGIC);
6855 vector<PWire*>*tmp = new vector<PWire*>(1);
6860 | K_reg IDENTIFIER ';'
6861 { perm_string pname = lex_strings.make($2);
6862 PWire*pp = new PWire(pname, NetNet::REG, NetNet::PIMPLICIT, IVL_VT_LOGIC);
6863 vector<PWire*>*tmp = new vector<PWire*>(1);
6868 | K_reg K_output IDENTIFIER ';'
6869 { perm_string pname = lex_strings.make($3);
6870 PWire*pp = new PWire(pname, NetNet::REG, NetNet::POUTPUT, IVL_VT_LOGIC);
6871 vector<PWire*>*tmp = new vector<PWire*>(1);
6881 | udp_port_decls udp_port_decl
6882 { vector<PWire*>*tmp = $1;
6883 size_t s1 = $1->size();
6884 tmp->resize(s1+$2->size());
6885 for (size_t idx = 0 ; idx < $2->size() ; idx += 1)
6886 tmp->at(s1+idx) = $2->at(idx);
6894 { list<perm_string>*tmp = new list<perm_string>;
6895 tmp->push_back(lex_strings.make($1));
6899 | udp_port_list ',' IDENTIFIER
6900 { list<perm_string>*tmp = $1;
6901 tmp->push_back(lex_strings.make($3));
6907 udp_reg_opt: K_reg { $$ = true; } | { $$ = false; };
6909 udp_initial_expr_opt
6910 : '=' expression { $$ = $2; }
6914 udp_input_declaration_list
6915 : K_input IDENTIFIER
6916 { list<perm_string>*tmp = new list<perm_string>;
6917 tmp->push_back(lex_strings.make($2));
6921 | udp_input_declaration_list ',' K_input IDENTIFIER
6922 { list<perm_string>*tmp = $1;
6923 tmp->push_back(lex_strings.make($4));
6930 /* This is the syntax for primitives that uses the IEEE1364-1995
6931 format. The ports are simply names in the port list, and the
6932 declarations are in the body. */
6934 : K_primitive IDENTIFIER '(' udp_port_list ')' ';'
6938 K_endprimitive endlabel_opt
6940 { perm_string tmp2 = lex_strings.make($2);
6941 pform_make_udp(tmp2, $4, $7, $9, $8,
6942 @2.text, @2.first_line);
6944 if (strcmp($2,$11) != 0) {
6945 yyerror(@11, "error: End label doesn't match "
6948 if (! gn_system_verilog()) {
6949 yyerror(@11, "error: Primitive end labels "
6950 "require SystemVerilog.");
6957 /* This is the syntax for IEEE1364-2001 format definitions. The port
6958 names and declarations are all in the parameter list. */
6960 | K_primitive IDENTIFIER
6961 '(' K_output udp_reg_opt IDENTIFIER udp_initial_expr_opt ','
6962 udp_input_declaration_list ')' ';'
6964 K_endprimitive endlabel_opt
6966 { perm_string tmp2 = lex_strings.make($2);
6967 perm_string tmp6 = lex_strings.make($6);
6968 pform_make_udp(tmp2, $5, tmp6, $7, $9, $12,
6969 @2.text, @2.first_line);
6971 if (strcmp($2,$14) != 0) {
6972 yyerror(@14, "error: End label doesn't match "
6975 if (! gn_system_verilog()) {
6976 yyerror(@14, "error: Primitive end labels "
6977 "require SystemVerilog.");
6986 /* Many keywords can be optional in the syntax, although their
6987 presence is significant. This is a fairly common pattern so
6988 collect those rules here. */
6990 K_packed_opt : K_packed { $$ = true; } | { $$ = false; } ;
6991 K_reg_opt : K_reg { $$ = true; } | { $$ = false; } ;
6992 K_static_opt : K_static { $$ = true; } | { $$ = false; } ;
6993 K_virtual_opt : K_virtual { $$ = true; } | { $$ = false; } ;