- '''module : attribute_list_opt module_start lifetime_opt IDENTIFIER _embed0_module module_package_import_list_opt module_parameter_port_list_opt module_port_list_opt module_attribute_foreign ';' _embed1_module timeunits_declaration_opt _embed2_module module_item_list_opt module_end _embed3_module endlabel_opt '''
- print('module_1', list(p))
- params = p[7]
- clsname = [Leaf(token.NAME, 'class'),
- Leaf(token.NAME, p[4], prefix=' '),
- Leaf(token.COLON, ':')]
- pass_stmt = Node(syms.pass_stmt, [Leaf(token.NAME, "pass"),])
- if params:
- params = [Leaf(token.LPAR, '(')] + params + [Leaf(token.RPAR, ')')]
- fn = [Leaf(token.NAME, 'def'),
- Leaf(token.NAME, '__init__', prefix=' '),
- Node(syms.parameters, params),
- Leaf(token.COLON, ':')]
- fndef = Node(syms.funcdef, fn)
- stmts = Node(syms.stmt, [fndef])
- else:
- stmts = Node(syms.small_stmt, [pass_stmt, Leaf(token.NEWLINE, '\n')])
- stmts = Node(syms.stmt, [stmts])
- suite = Node(syms.suite, [Leaf(token.NEWLINE, '\n'),
- Leaf(token.INDENT, ' '),
- stmts,
- Leaf(token.DEDENT, '')
- ])
- clsdecl = Node(syms.classdef, clsname + [suite],
- prefix='', fixers_applied=[])
- clsdecl = Node(syms.compound_stmt, [clsdecl])
- print ("clsdecl", repr(clsdecl))
- print ("clsstr:")
- print (str(clsdecl))
- p[0] = clsdecl
- # { // Last step: check any closing name. This is done late so
- # // that the parser can look ahead to detect the present
- # // endlabel_opt but still have the pform_endmodule() called
- # // early enough that the lexor can know we are outside the
- # // module.
- # if ($17) {
- # if (strcmp($4,$17) != 0) {
- # switch ($2) {
- # case K_module:
- # yyerror(@17, "error: End label doesn't match "
- # "module name.");
- # break;
- # case K_program:
- # yyerror(@17, "error: End label doesn't match "
- # "program name.");
- # break;
- # case K_interface:
- # yyerror(@17, "error: End label doesn't match "
- # "interface name.");
- # break;
- # default:
- # break;
- # }
- # }
- # if (($2 == K_module) && (! gn_system_verilog())) {
- # yyerror(@8, "error: Module end labels require "
- # "SystemVerilog.");
- # }
- # delete[]$17;
- # }
- # delete[]$4;
- # }