git.libre-soc.org Git - soclayout.git/history - experiments10

2021-06-05	Luke Kenneth Casso...	sort out clock names in experiments10_verilog	blob \| commitdiff \| raw
2021-06-05	Luke Kenneth Casso...	add dummy (fake) PLL to experiments10_verilog for testing	blob \| commitdiff \| raw \| diff to current
2021-04-13	Luke Kenneth Casso...	whoops forgot settings.py	blob \| commitdiff \| raw \| diff to current
2021-04-12	Luke Kenneth Casso...	set routingGauge manually	blob \| commitdiff \| raw \| diff to current
2021-04-12	Luke Kenneth Casso...	include (but do not use) FreePDK45 in experiments10	blob \| commitdiff \| raw \| diff to current
2021-04-12	Luke Kenneth Casso...	rename sys_clk in adder test experiments10_verilog...	blob \| commitdiff \| raw \| diff to current
2021-04-12	Luke Kenneth Casso...	rename JTAG port in adder test experiments10_verilog...	blob \| commitdiff \| raw \| diff to current
2021-04-12	Luke Kenneth Casso...	back to "working" verilog add	blob \| commitdiff \| raw \| diff to current
2021-04-09	Luke Kenneth Casso...	whitespace cleanup	blob \| commitdiff \| raw \| diff to current
2021-04-09	Luke Kenneth Casso...	rename design of experiments10 to match ls180 chip...	blob \| commitdiff \| raw \| diff to current
2021-04-02	Luke Kenneth Casso...	experiment with nmigen verilog generation	blob \| commitdiff \| raw \| diff to current