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simulation pads naming corrections for HyperRAMPads
[lambdasoc.git]
/
lambdasoc
/
periph
/
hyperram.py
2022-04-12
Luke Kenneth Casso...
simulation pads naming corrections for HyperRAMPads
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2022-03-28
Luke Kenneth Casso...
work through the CSns to give the appearance of having...
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2022-03-28
Luke Kenneth Casso...
add cs_latch as a peer of bus_latch in case the address...
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2022-03-28
Luke Kenneth Casso...
minor simplification of hyperram: using constants
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2022-03-28
Luke Kenneth Casso...
extend cs in hyperram to multiple bits
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2022-03-27
Luke Kenneth Casso...
update code-comments
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2022-03-27
Luke Kenneth Casso...
add reset pad to hyperram, should be set externally
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2022-03-26
Luke Kenneth Casso...
hyperram CS inverted (corrected)
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2022-03-26
Luke Kenneth Casso...
sort out hyperram ports down to test class
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2022-03-25
Luke Kenneth Casso...
fix attributes, sort out address
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2022-03-19
Luke Kenneth Casso...
rename hyperram clk pads to "ck"
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2022-03-18
Luke Kenneth Casso...
add ports function to HyperRAMPHY
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2022-03-18
Luke Kenneth Casso...
rename TestHyperRAMPHY to just HyperRAMPHY
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2022-03-18
Luke Kenneth Casso...
move HyperRAMPads and Test PHY to hyperram.py module
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2022-03-18
Luke Kenneth Casso...
remove redundant implementation of migen "timeline"
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2022-03-18
Luke Kenneth Casso...
document useful "add_extension" for HyperRAM PMODs
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2022-03-16
Luke Kenneth Casso...
update HyperRAM module and add unit test
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2022-03-15
Luke Kenneth Casso...
add first version of hyperram.py
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