must not delay ack to wb request in SRAM
[nmigen-soc.git] / nmigen_soc / wishbone /
2020-10-01 Luke Kenneth Casso... must not delay ack to wb request in SRAM master 24jan2021_ls180
2020-09-22 Luke Kenneth Casso... add (dummy) src_loc_at parameter
2020-08-04 Luke Kenneth Casso... test in sram for deliberately delaying response
2020-07-19 Luke Kenneth Casso... cannot use shape()[0] - must use width property
2020-06-26 Luke Kenneth Casso... write-enable sram into common wen signal, use that...
2020-06-20 Luke Kenneth Casso... add assertion checking bus write against memory write...
2020-06-20 Luke Kenneth Casso... avoid looking like a singleton pattern
2020-06-20 Luke Kenneth Casso... spelling correctinos
2020-06-20 Luke Kenneth Casso... import error
2020-06-20 Luke Kenneth Casso... resolve internal (nmigen_soc) imports
2020-06-20 Luke Kenneth Casso... fix nmigen imports
2020-06-20 Luke Kenneth Casso... more declaration of singleton objects
2020-06-20 Luke Kenneth Casso... whitespace error somehow
2020-06-19 Luke Kenneth Casso... more whitespace cleanup
2020-06-19 Luke Kenneth Casso... comment cleanup
2020-06-19 Luke Kenneth Casso... autopep8 cleanup
2020-06-19 Luke Kenneth Casso... whitespace cleanup
2020-03-01 Harry Howishbone: fix SRAM; improve tests for Decoder & Arbiter wishbone_interconnect
2020-01-30 Harry Howishbone: fix docstring & unneeded parameter for Interc...
2020-01-29 Harry Howishbone.bus: borrow & re-design Arbiter from 'jfng...
2020-01-29 Harry Howishbone: fix that RoundRobin might assert CYC indefinitely
2020-01-29 Harry Howishbone: optimise SRAM addr_width
2020-01-29 Harry Howishbone: add Arbiter, RoundRobin, SRAM, InterconnectShared
2020-01-22 Jean-François Nguyenwishbone.bus: add Arbiter.
2019-10-26 whitequarkwishbone.bus: add Decoder.
2019-10-26 whitequarkwishbone.bus.Interface: add support for LOCK_IO signal.
2019-10-25 whitequarkwishbone.bus: add Interface.