add in extra delay-for-core in ECP5CRG
[ls2.git] / src / ecp5_crg.py
2022-04-16 Luke Kenneth Casso... add in extra delay-for-core in ECP5CRG
2022-04-15 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2022-04-15 Luke Kenneth Casso... checking simulation of Async DDR3
2022-04-15 Luke Kenneth Casso... reorg of the ECP5 Clock-Reset to be able to add
2022-04-14 Luke Kenneth Casso... add new dram_clk_freq argument which does nothing for now
2022-04-14 Luke Kenneth Casso... add an extra domain dramsync2x in preparation for
2022-04-14 Luke Kenneth Casso... move 2x-clock-and-dividing into separate function in...
2022-04-10 Luke Kenneth Casso... Revert "Wire up missing CRG / DDR3 clock control /...
2022-04-10 Luke Kenneth Casso... Revert "Put sysclk2x back under system reset control"
2022-04-10 Raptor Engineering... Put sysclk2x back under system reset control
2022-04-09 Raptor Engineering... Wire up missing CRG / DDR3 clock control / reset signals
2022-03-26 Luke Kenneth Casso... reduce power-on-delay bits to 2 for icarus sim ecp5
2022-03-25 Luke Kenneth Casso... rename ECP5 CRG, move source, remove duplicate version