split out addstages to separate module
[ieee754fpu.git] / src / add / fpadd / addstages.py
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
3 # 2013-12-12
4
5 from nmigen import Module, Signal, Cat, Mux, Array, Const
6 from nmigen.lib.coding import PriorityEncoder
7 from nmigen.cli import main, verilog
8 from math import log
9
10 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
11 from fpbase import MultiShiftRMerge, Trigger
12 from singlepipe import (ControlBase, StageChain, UnbufferedPipeline,
13 PassThroughStage)
14 from multipipe import CombMuxOutPipe
15 from multipipe import PriorityCombMuxInPipe
16
17 from fpbase import FPState, FPID
18 from fpcommon.denorm import FPSCData
19 from fpcommon.postcalc import FPAddStage1Data
20 from fpadd.align import FPAddAlignSingleMod
21 from fpadd.add0 import (FPAddStage0Data, FPAddStage0Mod, FPAddStage0)
22 from fpadd.add1 import (FPAddStage1Mod, FPAddStage1)
23
24
25 class FPAddAlignSingleAdd(FPState, UnbufferedPipeline):
26
27 def __init__(self, width, id_wid):
28 FPState.__init__(self, "align")
29 self.width = width
30 self.id_wid = id_wid
31 UnbufferedPipeline.__init__(self, self) # pipeline is its own stage
32 self.a1o = self.ospec()
33
34 def ispec(self):
35 return FPSCData(self.width, self.id_wid)
36
37 def ospec(self):
38 return FPAddStage1Data(self.width, self.id_wid) # AddStage1 ospec
39
40 def setup(self, m, i):
41 """ links module to inputs and outputs
42 """
43
44 # chain AddAlignSingle, AddStage0 and AddStage1
45 mod = FPAddAlignSingleMod(self.width, self.id_wid)
46 a0mod = FPAddStage0Mod(self.width, self.id_wid)
47 a1mod = FPAddStage1Mod(self.width, self.id_wid)
48
49 chain = StageChain([mod, a0mod, a1mod])
50 chain.setup(m, i)
51
52 self.o = a1mod.o
53
54 def process(self, i):
55 return self.o
56
57 def action(self, m):
58 m.d.sync += self.a1o.eq(self.process(None))
59 m.next = "normalise_1"
60
61