src/add/record_experiment.py

   1 from nmigen import Module, Signal, Mux, Const
   2 from nmigen.hdl.rec import Record, Layout, DIR_NONE
   3 from nmigen.compat.sim import run_simulation
   4 from nmigen.cli import verilog, rtlil
   5 from nmigen.compat.fhdl.bitcontainer import value_bits_sign
   6 from singlepipe import flatten, RecordObject
   7
   8
   9 class RecordTest:
  10
  11     def __init__(self):
  12         self.r1 = RecordObject()
  13         self.r1.sig1 = Signal(32)
  14         self.r1.r2 = RecordObject()
  15         self.r1.r2.sig2 = Signal(32)
  16         self.r1.r3 = RecordObject()
  17         self.r1.r3.sig3 = Signal(32)
  18         self.sig123 = Signal(96)
  19
  20     def elaborate(self, platform):
  21         m = Module()
  22
  23         sig1 = Signal(32)
  24         m.d.comb += sig1.eq(self.r1.sig1)
  25         sig2 = Signal(32)
  26         m.d.comb += sig2.eq(self.r1.r2.sig2)
  27
  28         print (self.r1.fields)
  29         print (self.r1.shape())
  30         print (len(self.r1))
  31         m.d.comb += self.sig123.eq(flatten(self.r1))
  32
  33         return m
  34
  35
  36 def testbench(dut):
  37     yield dut.r1.sig1.eq(5)
  38     yield dut.r1.r2.sig2.eq(10)
  39
  40     sig1 = yield dut.r1.sig1
  41     assert sig1 == 5
  42     sig2 = yield dut.r1.r2.sig2
  43     assert sig2 == 10
  44
  45
  46
  47 ######################################################################
  48 # Unit Tests
  49 ######################################################################
  50
  51 if __name__ == '__main__':
  52     print ("test 1")
  53     dut = RecordTest()
  54     run_simulation(dut, testbench(dut), vcd_name="test_record1.vcd")
  55     vl = rtlil.convert(dut, ports=[dut.sig123, dut.r1.sig1, dut.r1.r2.sig2])
  56     with open("test_record1.il", "w") as f:
  57         f.write(vl)
  58