src/ieee754/add/test_dual.py

   1 from sfpy import Float32
   2 from nmigen.compat.sim import run_simulation
   3 from dual_add_experiment import ALU
   4
   5
   6 def get_case(dut, a, b, c):
   7     yield dut.a.v.eq(a)
   8     yield dut.a.stb.eq(1)
   9     yield
  10     yield
  11     a_ack = (yield dut.a.ack)
  12     assert a_ack == 0
  13
  14     yield dut.a.stb.eq(0)
  15
  16     yield dut.b.v.eq(b)
  17     yield dut.b.stb.eq(1)
  18     yield
  19     yield
  20     b_ack = (yield dut.b.ack)
  21     assert b_ack == 0
  22
  23     yield dut.b.stb.eq(0)
  24
  25     yield dut.c.v.eq(c)
  26     yield dut.c.stb.eq(1)
  27     yield
  28     yield
  29     c_ack = (yield dut.c.ack)
  30     assert c_ack == 0
  31
  32     yield dut.c.stb.eq(0)
  33
  34     yield dut.z.ack.eq(1)
  35
  36     while True:
  37         out_z_stb = (yield dut.z.stb)
  38         if not out_z_stb:
  39             yield
  40             continue
  41
  42         out_z = yield dut.z.v
  43
  44         yield dut.z.ack.eq(0)
  45         break
  46
  47     return out_z
  48
  49 def check_case(dut, a, b, c, z):
  50     out_z = yield from get_case(dut, a, b, c)
  51     assert out_z == z, "Output z 0x%x != 0x%x" % (out_z, z)
  52
  53 def testbench(dut):
  54     yield from check_case(dut, 0, 0, 0, 0)
  55     yield from check_case(dut, 0x3F800000, 0x40000000, 0xc0000000, 0x3F800000)
  56
  57 if __name__ == '__main__':
  58     dut = ALU(width=32)
  59     run_simulation(dut, testbench(dut), vcd_name="test_dual_add.vcd")
  60