src/nmutil/latch.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Signal, Module, Elaboratable
   4
   5
   6 class SRLatch(Elaboratable):
   7     def __init__(self):
   8         self.s = Signal(reset_less=True)
   9         self.r = Signal(reset_less=True)
  10         self.q = Signal(reset_less=True)
  11         self.qn = Signal(reset_less=True)
  12
  13     def elaborate(self, platform):
  14         m = Module()
  15         q_int = Signal(reset_less=True)
  16
  17         with m.If(self.s):
  18             m.d.sync += q_int.eq(1)
  19         with m.Elif(self.r):
  20             m.d.sync += q_int.eq(0)
  21
  22         m.d.comb += self.q.eq(q_int)
  23         m.d.comb += self.qn.eq(~q_int)
  24
  25         return m
  26
  27     def ports(self):
  28         return self.s, self.r, self.q, self.qn
  29
  30
  31 def sr_sim(dut):
  32     yield dut.s.eq(0)
  33     yield dut.r.eq(0)
  34     yield
  35     yield
  36     yield
  37     yield dut.s.eq(1)
  38     yield
  39     yield
  40     yield
  41     yield dut.s.eq(0)
  42     yield
  43     yield
  44     yield
  45     yield dut.r.eq(1)
  46     yield
  47     yield
  48     yield
  49     yield dut.r.eq(0)
  50     yield
  51     yield
  52     yield
  53
  54 def test_sr():
  55     dut = SRLatch()
  56     vl = rtlil.convert(dut, ports=dut.ports())
  57     with open("test_srlatch.il", "w") as f:
  58         f.write(vl)
  59
  60     run_simulation(dut, sr_sim(dut), vcd_name='test_srlatch.vcd')
  61
  62 if __name__ == '__main__':
  63     test_sr()