corrections to ld-st cell and sparse-matrix

diff --git a/src/scoreboard/ldst_dep_cell.py b/src/scoreboard/ldst_dep_cell.py
index f8d6230855b4e798d6ff7e3dae2cd37b382afe73..40e1ffbc4d8d724961ec46da29569e12ae64ce85 100644 (file)
--- a/src/scoreboard/ldst_dep_cell.py
+++ b/src/scoreboard/ldst_dep_cell.py
@@ -13,10 +13,6 @@ from nmutil.latch import SRLatch
 
 class LDSTDepCell(Elaboratable):
     """ implements 11.4.12 mitch alsup load/store dependence cell, p45
-
-        note: the load-hold-store / store-hold-load both come through from
-        the previous cell and accumulate using ORing to create priority
-        picking (in the sparse-matrix, which is where the cells are wired up)
     """
     def __init__(self):
         # inputs
@@ -26,8 +22,6 @@ class LDSTDepCell(Elaboratable):
 
         self.load_hit_i = Signal(reset_less=True) # load hit in (right)
         self.stwd_hit_i = Signal(reset_less=True) # store w/ data hit in (right)
-        self.ld_hold_st_i = Signal(reset_less=True) # load holds st in (right)
-        self.st_hold_ld_i = Signal(reset_less=True) # st holds load in (right)
 
         # outputs (latched rd/wr pend)
         self.ld_hold_st_o = Signal(reset_less=True) # load holds st out (left)
@@ -51,10 +45,8 @@ class LDSTDepCell(Elaboratable):
         m.d.comb += raw_l.r.eq(self.stor_i) # reset on ST
 
         # Hold results (read out horizontally, accumulate in OR fashion)
-        lhs = war_l.qn & self.load_hit_i
-        shl = raw_l.qn & self.stwd_hit_i
-        m.d.comb += self.ld_hold_st_o.eq(self.ld_hold_st_i | lhs)
-        m.d.comb += self.st_hold_ld_o.eq(self.st_hold_ld_i | shl)
+        m.d.comb += self.ld_hold_st_o.eq(war_l.qn & self.load_hit_i)
+        m.d.comb += self.st_hold_ld_o.eq(raw_l.qn & self.stwd_hit_i)
 
         return m
 
@@ -64,8 +56,6 @@ class LDSTDepCell(Elaboratable):
         yield self.issue_i
         yield self.load_hit_i
         yield self.stwd_hit_i
-        yield self.ld_hold_st_i
-        yield self.st_hold_ld_i
         yield self.ld_hold_st_o
         yield self.st_hold_ld_o
                 

diff --git a/src/scoreboard/ldst_matrix.py b/src/scoreboard/ldst_matrix.py
index 07a832d63c75b477d86794d332d322f05502086a..b872155d8f05945a49c5aa43238a3507ab129944 100644 (file)
--- a/src/scoreboard/ldst_matrix.py
+++ b/src/scoreboard/ldst_matrix.py
@@ -41,8 +41,8 @@ class LDSTDepMatrix(Elaboratable):
         self.stwd_hit_i = Signal(n_ldst, reset_less=True) # store w/data hit in
 
         # outputs
-        self.ld_hold_st_o = Signal(n_ldst, reset_less=True) # load holds st out
-        self.st_hold_ld_o = Signal(n_ldst, reset_less=True) # st holds load out
+        self.ld_hold_st_o = Signal(reset_less=True) # load holds st out
+        self.st_hold_ld_o = Signal(reset_less=True) # st holds load out
 
     def elaborate(self, platform):
         m = Module()
@@ -57,8 +57,6 @@ class LDSTDepMatrix(Elaboratable):
         # ---
         # connect Function Unit vector
         # ---
-        lhs = Const(0) # start at const 0
-        shl = Const(0) # (does no harm)
         lhs_l = []
         shl_l = []
         load_l = []
@@ -68,15 +66,9 @@ class LDSTDepMatrix(Elaboratable):
         sh_l = []
         for fu in range(self.n_ldst):
             dc = dm[fu]
-            # connect up the load/hold/store cell in/out (starts as a const)
-            m.d.comb += [dc.ld_hold_st_i.eq(lhs),
-                         dc.st_hold_ld_i.eq(shl)
-                        ]
-            lhs = dc.ld_hold_st_o
-            shl = dc.st_hold_ld_o
             # accumulate load-hold-store / store-hold-load bits
-            lhs_l.append(lhs)
-            shl_l.append(shl)
+            lhs_l.append(dc.ld_hold_st_o)
+            shl_l.append(dc.st_hold_ld_o)
             # accumulate inputs (for Cat'ing later) - TODO: must be a better way
             load_l.append(dc.load_i)
             stor_l.append(dc.stor_i)
@@ -92,8 +84,8 @@ class LDSTDepMatrix(Elaboratable):
                      Cat(*sh_l).eq(self.stwd_hit_i),
                     ]
         # set the load-hold-store / store-hold-load OR-accumulated outputs
-        m.d.comb += self.ld_hold_st_o.eq(Cat(*lhs_l))
-        m.d.comb += self.st_hold_ld_o.eq(Cat(*shl_l))
+        m.d.comb += self.ld_hold_st_o.eq(Cat(*lhs_l).bool())
+        m.d.comb += self.st_hold_ld_o.eq(Cat(*shl_l).bool())
 
         return m