add function unit read/write pending

diff --git a/src/scoreboard/dependence_cell.py b/src/scoreboard/dependence_cell.py
index 3624d1a48d1da1c6dd850c769260f97d5ee8ed68..1c8a0095967e51f4e9dda213617d4413b67c4cb9 100644 (file)
--- a/src/scoreboard/dependence_cell.py
+++ b/src/scoreboard/dependence_cell.py
@@ -45,15 +45,15 @@ class DependenceCell(Elaboratable):
         m.d.sync += src2_l.r.eq(self.go_read_i)
 
         # FU "Forward Progress" (read out horizontally)
-        m.d.comb += self.dest_rsel_o.eq(dest_l.qn & self.go_write_i)
-        m.d.comb += self.src1_rsel_o.eq(src1_l.qn & self.go_read_i)
-        m.d.comb += self.src2_rsel_o.eq(src2_l.qn & self.go_read_i)
-
-        # Register File Select (read out vertically)
         m.d.comb += self.dest_fwd_o.eq(dest_l.qn & self.dest_i)
         m.d.comb += self.src1_fwd_o.eq(src1_l.qn & self.src1_i)
         m.d.comb += self.src2_fwd_o.eq(src2_l.qn & self.src2_i)
 
+        # Register File Select (read out vertically)
+        m.d.comb += self.dest_rsel_o.eq(dest_l.qn & self.go_write_i)
+        m.d.comb += self.src1_rsel_o.eq(src1_l.qn & self.go_read_i)
+        m.d.comb += self.src2_rsel_o.eq(src2_l.qn & self.go_read_i)
+
         return m
 
     def __iter__(self):

diff --git a/src/scoreboard/fu_wr_pending.py b/src/scoreboard/fu_wr_pending.py
new file mode 100644 (file)
index 0000000..9bba20e
--- /dev/null
+++ b/src/scoreboard/fu_wr_pending.py
@@ -0,0 +1,20 @@
+from nmigen import Elaboratable, Module, Signal
+
+
+class FUReadWritePending(Elaboratable):
+    def __init__(self, reg_count):
+        self.reg_count = reg_count
+        self.dest_fwd_i = Signal(fu_count, reset_less=True)
+        self.src1_fwd_i = Signal(fu_count, reset_less=True)
+        self.src2_fwd_i = Signal(fu_count, reset_less=True)
+
+        self.wr_pend_o = Signal(reset_less=True)
+        self.rd_pend_o = Signal(reset_less=True)
+
+    def elaboratable(self, platform):
+        m = Module()
+        srces = Cat(self.src1_fwd_i, self.src2_fwd_i)
+        m.d.comb += self.wr_pend_o.eq(self.dest_fwd_i.bool())
+        m.d.comb += self.rd_pend_o.eq(srces.bool() 
+        return m
+

diff --git a/src/scoreboard/reg_select.py b/src/scoreboard/reg_select.py
index 9d16741b61e156cd030e125d3627ea7139c13222..04deaac549c4f62d3673363c4e4117b946751b21 100644 (file)
--- a/src/scoreboard/reg_select.py
+++ b/src/scoreboard/reg_select.py
@@ -1,4 +1,5 @@
-from nmigen import Elaboratable, Module, Array, Signal
+from nmigen import Elaboratable, Module, Signal
+
 
 class RegReservation(Elaboratable):
     def __init__(self, fu_count):