get test_add working after reorg

diff --git a/src/ieee754/add/concurrentunit.py b/src/ieee754/add/concurrentunit.py
deleted file mode 100644 (file)
index 82b81ff..0000000
--- a/src/ieee754/add/concurrentunit.py
+++ /dev/null
@@ -1,67 +0,0 @@
-# IEEE Floating Point Adder (Single Precision)
-# Copyright (C) Jonathan P Dawson 2013
-# 2013-12-12
-
-from math import log
-from nmigen import Module
-from nmigen.cli import main, verilog
-
-from nmutil.singlepipe import PassThroughStage
-from nmutil.multipipe import CombMuxOutPipe
-from nmutil.multipipe import PriorityCombMuxInPipe
-
-
-def num_bits(n):
-    return int(log(n) / log(2))
-
-class FPADDInMuxPipe(PriorityCombMuxInPipe):
-    def __init__(self, num_rows, iospecfn):
-        self.num_rows = num_rows
-        stage = PassThroughStage(iospecfn)
-        PriorityCombMuxInPipe.__init__(self, stage, p_len=self.num_rows)
-
-
-class FPADDMuxOutPipe(CombMuxOutPipe):
-    def __init__(self, num_rows, iospecfn):
-        self.num_rows = num_rows
-        stage = PassThroughStage(iospecfn)
-        CombMuxOutPipe.__init__(self, stage, n_len=self.num_rows)
-
-
-class ReservationStations:
-    """ Reservation-Station pipeline
-
-        Input: num_rows - number of input and output Reservation Stations
-
-        Requires: the addition of an "alu" object, an i_specfn and an o_specfn
-
-        * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
-        * ALU pipeline
-        * fan-out on outputs (an array of FPPackData: z,mid)
-
-        Fan-in and Fan-out are combinatorial.
-    """
-    def __init__(self, num_rows):
-        self.num_rows = num_rows
-        self.inpipe = FPADDInMuxPipe(num_rows, self.i_specfn)   # fan-in
-        self.outpipe = FPADDMuxOutPipe(num_rows, self.o_specfn) # fan-out
-
-        self.p = self.inpipe.p  # kinda annoying,
-        self.n = self.outpipe.n # use pipe in/out as this class in/out
-        self._ports = self.inpipe.ports() + self.outpipe.ports()
-
-    def elaborate(self, platform):
-        m = Module()
-        m.submodules.inpipe = self.inpipe
-        m.submodules.alu = self.alu
-        m.submodules.outpipe = self.outpipe
-
-        m.d.comb += self.inpipe.n.connect_to_next(self.alu.p)
-        m.d.comb += self.alu.connect_to_next(self.outpipe)
-
-        return m
-
-    def ports(self):
-        return self._ports
-
-

diff --git a/src/ieee754/fpadd/pipeline.py b/src/ieee754/fpadd/pipeline.py
index eea893552047d772f8ba7adf930db3a6e729e118..7b37a6877d797ee2b0a0d4f03556ec3c151e4981 100644 (file)
--- a/src/ieee754/fpadd/pipeline.py
+++ b/src/ieee754/fpadd/pipeline.py
@@ -8,6 +8,7 @@ from nmigen.cli import main, verilog
 from nmutil.singlepipe import (ControlBase, SimpleHandshake, PassThroughStage)
 from nmutil.multipipe import CombMuxOutPipe
 from nmutil.multipipe import PriorityCombMuxInPipe
 from nmutil.singlepipe import (ControlBase, SimpleHandshake, PassThroughStage)
 from nmutil.multipipe import CombMuxOutPipe
 from nmutil.multipipe import PriorityCombMuxInPipe

+from nmutil.concurrentunit import ReservationStations, num_bits

 
 from ieee754.fpcommon.getop import FPADDBaseData
 from ieee754.fpcommon.denorm import FPSCData
 
 from ieee754.fpcommon.getop import FPADDBaseData
 from ieee754.fpcommon.denorm import FPSCData


@@ -16,7 +17,6 @@ from ieee754.fpcommon.normtopack import FPNormToPack
 from .specialcases import FPAddSpecialCasesDeNorm
 from .addstages import FPAddAlignSingleAdd
 
 from .specialcases import FPAddSpecialCasesDeNorm
 from .addstages import FPAddAlignSingleAdd
 

-from concurrentunit import ReservationStations, num_bits

 
 
 class FPADDBasePipe(ControlBase):
 
 
 class FPADDBasePipe(ControlBase):

diff --git a/src/ieee754/fpadd/test/test_add.py b/src/ieee754/fpadd/test/test_add.py
index 35503bed0375e2145f7ddb089fc73ad4d2610a2a..f09804cd21e4e2bd05916c962f5738d3537570e3 100644 (file)
--- a/src/ieee754/fpadd/test/test_add.py
+++ b/src/ieee754/fpadd/test/test_add.py
@@ -5,7 +5,7 @@ from nmigen.compat.sim import run_simulation
 
 from ieee754.fpadd.nmigen_add_experiment import FPADD
 
 
 from ieee754.fpadd.nmigen_add_experiment import FPADD
 

-from iee754.fpcommon.unit_test_single import (get_mantissa, get_exponent,
+from ieee754.fpcommon.test.unit_test_single import (get_mantissa, get_exponent,

                                 get_sign, is_nan,
                                 is_inf, is_pos_inf, is_neg_inf,
                                 match, get_rs_case, check_rs_case, run_test,
                                 get_sign, is_nan,
                                 is_inf, is_pos_inf, is_neg_inf,
                                 match, get_rs_case, check_rs_case, run_test,

diff --git a/src/nmutil/concurrentunit.py b/src/nmutil/concurrentunit.py
new file mode 100644 (file)
index 0000000..82b81ff
--- /dev/null
+++ b/src/nmutil/concurrentunit.py
@@ -0,0 +1,67 @@
+# IEEE Floating Point Adder (Single Precision)
+# Copyright (C) Jonathan P Dawson 2013
+# 2013-12-12
+
+from math import log
+from nmigen import Module
+from nmigen.cli import main, verilog
+
+from nmutil.singlepipe import PassThroughStage
+from nmutil.multipipe import CombMuxOutPipe
+from nmutil.multipipe import PriorityCombMuxInPipe
+
+
+def num_bits(n):
+    return int(log(n) / log(2))
+
+class FPADDInMuxPipe(PriorityCombMuxInPipe):
+    def __init__(self, num_rows, iospecfn):
+        self.num_rows = num_rows
+        stage = PassThroughStage(iospecfn)
+        PriorityCombMuxInPipe.__init__(self, stage, p_len=self.num_rows)
+
+
+class FPADDMuxOutPipe(CombMuxOutPipe):
+    def __init__(self, num_rows, iospecfn):
+        self.num_rows = num_rows
+        stage = PassThroughStage(iospecfn)
+        CombMuxOutPipe.__init__(self, stage, n_len=self.num_rows)
+
+
+class ReservationStations:
+    """ Reservation-Station pipeline
+
+        Input: num_rows - number of input and output Reservation Stations
+
+        Requires: the addition of an "alu" object, an i_specfn and an o_specfn
+
+        * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
+        * ALU pipeline
+        * fan-out on outputs (an array of FPPackData: z,mid)
+
+        Fan-in and Fan-out are combinatorial.
+    """
+    def __init__(self, num_rows):
+        self.num_rows = num_rows
+        self.inpipe = FPADDInMuxPipe(num_rows, self.i_specfn)   # fan-in
+        self.outpipe = FPADDMuxOutPipe(num_rows, self.o_specfn) # fan-out
+
+        self.p = self.inpipe.p  # kinda annoying,
+        self.n = self.outpipe.n # use pipe in/out as this class in/out
+        self._ports = self.inpipe.ports() + self.outpipe.ports()
+
+    def elaborate(self, platform):
+        m = Module()
+        m.submodules.inpipe = self.inpipe
+        m.submodules.alu = self.alu
+        m.submodules.outpipe = self.outpipe
+
+        m.d.comb += self.inpipe.n.connect_to_next(self.alu.p)
+        m.d.comb += self.alu.connect_to_next(self.outpipe)
+
+        return m
+
+    def ports(self):
+        return self._ports
+
+