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LD/ST latches are async (clockless)
2019-04-30 Aleksandar KostovicCreated the normalise function
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2019-04-29 Aleksandar KostovicTried to make final assignemnt of the sqrt
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2019-04-29 Aleksandar KostovicCreated small test for decode_fp32 function
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2019-04-28 Aleksandar KostovicCreated two nested for loops for testing
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2019-04-28 Aleksandar KostovicCommented the right function
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2019-04-28 Aleksandar KostovicCreated the main function
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2019-04-28 Aleksandar KostovicAdapted the C version of sqrt to python
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2019-04-27 Aleksandar KostovicRemoved left semicolons
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2019-04-27 Aleksandar KostovicNemoved the example number
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2019-04-27 Aleksandar KostovicCreated the sqrt function found on wikipedia page
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2019-04-27 Aleksandar KostovicVery simple function for sqrt
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2019-04-12 Aleksandar KostovicCreate fsqrt.py file and put the verilog code in comments...
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2019-04-05 Aleksandar KostovicMerge branch 'master' of ssh://libre-riscv.org:922...
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2019-04-05 Aleksandar KostovicFixed the error when runing unit test
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2019-04-05 Aleksandar KostovicFixed indentation issiues with fmul.py
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2019-04-04 Aleksandar KostovicAdd m.d.sync return to get_a and get_b cases
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2019-03-15 Aleksandar KostovicRemoved unnecessary files
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2019-03-15 Aleksandar KostovicMerge branch 'master' of ssh://libre-riscv.org:922...
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2019-03-15 Aleksandar KostovicOnly Imported FPGetOp
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2019-03-13 Aleksandar KostovicStarted to update fmul.py to new conventions
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2019-02-20 Aleksandar KostovicRemove coments with verilog code
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2019-02-17 Aleksandar KostovicFinished the module states and added __main__
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2019-02-17 Aleksandar KostovicAdd more special cases to the module
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2019-02-17 Aleksandar KostovicAdded comment to explain a case
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2019-02-17 Aleksandar KostovicTranslated more of the special cases to nmigen
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2019-02-17 Aleksandar KostovicTranslated some of the special cases to nmigen
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2019-02-17 Aleksandar KostovicStarted to build module using functions instead plain...
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2019-02-17 Aleksandar KostovicStarted to translate special cases
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2019-02-17 Aleksandar KostovicDone unpack in nmigen
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2019-02-16 Aleksandar KostovicFixed typo in get_b state
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2019-02-16 Aleksandar KostovicDid get_b state in nmigen
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2019-02-16 Aleksandar KostovicDid get_a state in nmigen
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2019-02-16 Aleksandar KostovicMade a file and started to do porting from verilog...
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2019-02-14 Aleksandar KostovicTranslate put_z verilog case into nmigen
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2019-02-14 Aleksandar KostovicTranslate case from verilog to nmigen
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2019-02-14 Aleksandar KostovicMerge branch 'master' of ssh://libre-riscv.org:922...
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2019-02-14 Aleksandar KostovicTurned the normalise_2 verilog state into nmigen
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2019-02-14 Aleksandar KostovicMerge branch 'master' of ssh://libre-riscv.org:922...
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2019-02-14 Aleksandar KostovicTurned the add_1 verilog state into nmigen
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2019-02-14 Aleksandar KostovicTurned the add_0 verilog state into nmigen
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2019-02-13 Aleksandar KostovicReplicated unpack part of always block into nmigen
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