add PLL clock loop-back into CPU

diff --git a/libresoc/core.py b/libresoc/core.py
index 178ebe8bfb0f38af2b9342b85a9bb8c3b303014c..7ebbbddad282793ccf22d13964c90dd88b4fc418 100644 (file)
--- a/libresoc/core.py
+++ b/libresoc/core.py
@@ -186,6 +186,7 @@ class LibreSoC(CPU):
         self.platform     = platform
         self.variant      = variant
         self.reset        = Signal()
+        self.clk          = ClockSignal()
 
         irq_en = "noirq" not in variant
 
@@ -236,7 +237,7 @@ class LibreSoC(CPU):
 
         self.cpu_params = dict(
             # Clock / Reset
-            i_clk              = ClockSignal(),
+            i_clk              = self.clk,
             i_rst              = ResetSignal() | self.reset,
 
             # Monitoring / Debugging