projects / riscv-tests.git / commitdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: eebc9c3)
Changing the register mstatus is read into (#152)
authorSrivatsa Yogendra <36861801+srivatsa611y@users.noreply.github.com>
Tue, 21 Aug 2018 20:14:07 +0000 (13:14 -0700)
committerAndrew Waterman <aswaterman@gmail.com>
Tue, 21 Aug 2018 20:14:07 +0000 (13:14 -0700)
The mstatus reading overwrites the expected user mode cause value.

isa/rv64si/scall.S patch | blob | history

diff --git a/isa/rv64si/scall.S b/isa/rv64si/scall.S
index 0579806e9af0770cf7c04eb689e25ec29d055c9e..82f202a361836866ac69c4ab3e7cb392362c07d2 100644 (file)
--- a/isa/rv64si/scall.S
+++ b/isa/rv64si/scall.S
@@ -34,8 +34,8 @@ RVTEST_CODE_BEGIN
   # Otherwise, if in S mode, then U mode must exist and we don't need to check.
   li t0, MSTATUS_MPP
   csrc mstatus, t0
-  csrr t1, mstatus
-  and t0, t0, t1
+  csrr t2, mstatus
+  and t0, t0, t2
   beqz t0, 1f
 
   # If U mode doesn't exist, mcause should indicate ECALL from M mode.