Make sure that code is 4-byte aligned before disabling rvc (#100)

diff --git a/isa/rv64mi/ma_addr.S b/isa/rv64mi/ma_addr.S
index 2f4d96dea9dfcbd321d8e2fa7687e21084655119..721ac6afcf708f18026578615c3985cb06a30222 100644 (file)
--- a/isa/rv64mi/ma_addr.S
+++ b/isa/rv64mi/ma_addr.S
@@ -13,6 +13,7 @@
 RVTEST_RV64M
 RVTEST_CODE_BEGIN
 
+  .align 2
   .option norvc
 
   la s0, data

diff --git a/isa/rv64si/ma_fetch.S b/isa/rv64si/ma_fetch.S
index 594345687a83fc1436ae7cfc3e02bdfe7780fbb0..cd5a22d72077a768ff6e9753ec56c7e84fbc2990 100644 (file)
--- a/isa/rv64si/ma_fetch.S
+++ b/isa/rv64si/ma_fetch.S
@@ -23,6 +23,7 @@ RVTEST_CODE_BEGIN
   #define stvec_handler mtvec_handler
 #endif
 
+  .align 2
   .option norvc
 
   # Without RVC, the jalr should trap, and the handler will skip ahead.

diff --git a/isa/rv64uc/rvc.S b/isa/rv64uc/rvc.S
index b0766a9671abf7add918660a976d9003d11377e3..3629d1d021f8ba95e98639ebbfa45f608388c5a4 100644 (file)
--- a/isa/rv64uc/rvc.S
+++ b/isa/rv64uc/rvc.S
@@ -13,11 +13,12 @@
 RVTEST_RV64U
 RVTEST_CODE_BEGIN
 
+  .align 2
   .option push
   .option norvc
 
   #define RVC_TEST_CASE(n, r, v, code...) \
-    TEST_CASE (n, r, v, .option push; .option rvc; code; .option pop)
+    TEST_CASE (n, r, v, .option push; .option rvc; code; .align 2; .option pop)
 
   // Make sure fetching a 4-byte instruction across a page boundary works.
   li TESTNUM, 2

diff --git a/isa/rv64ui/jalr.S b/isa/rv64ui/jalr.S
index d63bbe206a7f41d72fdde61e67bdb541e2cfd579..f27005a5ee2cef96ecfaf4796ad8ac8503db616d 100644 (file)
--- a/isa/rv64ui/jalr.S
+++ b/isa/rv64ui/jalr.S
@@ -43,6 +43,7 @@ target_2:
   #-------------------------------------------------------------
 
   .option push
+  .align 2
   .option norvc
   TEST_CASE( 7, t0, 4, \
     li  t0, 1; \