Merge pull request #47 from riscv/debug-0.13

Debug 0.13 Tests

diff --git a/env b/env
index 70f5e06eef154a1eaeb65d3f034c1857771100ff..d7b2fdc9ed30163ac7e4f5cfc502710e862a112e 160000 (submodule)
--- a/env
+++ b/env
@@ -1 +1 @@
-Subproject commit 70f5e06eef154a1eaeb65d3f034c1857771100ff
+Subproject commit d7b2fdc9ed30163ac7e4f5cfc502710e862a112e

diff --git a/isa/rv64si/csr.S b/isa/rv64si/csr.S
index 13dbf2679545f9dda98bc74bad2d317486131c40..0576678d47171ea86b654a05d658f9f4ee1df719 100644 (file)
--- a/isa/rv64si/csr.S
+++ b/isa/rv64si/csr.S
@@ -24,6 +24,11 @@ RVTEST_CODE_BEGIN
   #define SSTATUS_SPP MSTATUS_MPP
 #endif
 
+  # For RV64, make sure UXL encodes RV64.  (UXL does not exist for RV32.)
+#if __riscv_xlen == 64
+  TEST_CASE(13, a0, SSTATUS_UXL & (SSTATUS_UXL << 1), csrr a0, sstatus; li a1, SSTATUS_UXL; and a0, a0, a1)
+#endif
+
   csrwi sscratch, 3
   TEST_CASE( 2, a0,         3, csrr a0, sscratch);
   TEST_CASE( 3, a1,         3, csrrci a1, sscratch, 1);

diff --git a/isa/rv64si/dirty.S b/isa/rv64si/dirty.S
index 17aa57f7145c67563d891772132f763d8a2e2205..783522c1ed76ba7a3ce32fe408aa86891d5e1e2c 100644 (file)
--- a/isa/rv64si/dirty.S
+++ b/isa/rv64si/dirty.S
@@ -28,7 +28,7 @@ RVTEST_CODE_BEGIN
   # Try a faulting store to make sure dirty bit is not set
   li TESTNUM, 2
   li t2, 1
-  sw t2, dummy - DRAM_BASE, t1
+  sw t2, dummy - DRAM_BASE, a0
 
   # Set SUM=1 so user memory access is permitted
   li TESTNUM, 3
@@ -40,7 +40,7 @@ RVTEST_CODE_BEGIN
   bnez t0, die
 
   # Try a non-faulting store to make sure dirty bit is set
-  sw t2, dummy - DRAM_BASE, t1
+  sw t2, dummy - DRAM_BASE, a0
 
   # Make sure it succeeded
   lw t0, dummy - DRAM_BASE
@@ -52,9 +52,22 @@ RVTEST_CODE_BEGIN
 
   # Make sure D bit is set
   lw t0, page_table_1
-  li t1, PTE_A | PTE_D
-  and t0, t0, t1
-  bne t0, t1, die
+  li a0, PTE_A | PTE_D
+  and t0, t0, a0
+  bne t0, a0, die
+
+  # Enter MPRV again
+  li t0, MSTATUS_MPRV
+  csrs mstatus, t0
+
+  # Make sure that superpage entries trap when PPN LSBs are set.
+  li TESTNUM, 4
+  lw a0, page_table_1 - DRAM_BASE
+  or a0, a0, 1 << PTE_PPN_SHIFT
+  sw a0, page_table_1 - DRAM_BASE, t0
+  sfence.vma
+  sw a0, page_table_1 - DRAM_BASE, t0
+  j die
   
   RVTEST_PASS
 
@@ -81,11 +94,20 @@ skip:
 1:
   li t1, 3
   bne TESTNUM, t1, 1f
-  # The implementation doesn't appear to set D bits in HW.  Skip the test,
-  # after making sure the D bit is clear.
+  # The implementation doesn't appear to set D bits in HW.
+  # Make sure the D bit really is clear.
   lw t0, page_table_1
   and t1, t0, PTE_D
   bnez t1, die
+  # Set the D bit.
+  or t0, t0, PTE_D
+  sw t0, page_table_1, t1
+  sfence.vma
+  mret
+
+1:
+  li t1, 4
+  bne TESTNUM, t1, 1f
   j pass
 
 1: